forked from luck/tmp_suning_uos_patched
9ab4650f71
Instead of reading the silicon version from ROM, we should read the SREV register from the IIM. Freescale has dropped all support for MX51 REV1.0, only MX51 REV 2.0 and 3.0 are valid. Signed-off-by: Dinh Nguyen <Dinh.Nguyen@freescale.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
252 lines
9.4 KiB
C
252 lines
9.4 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This contains i.MX27-specific hardware definitions. For those
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* hardware pieces that are common between i.MX21 and i.MX27, have a
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* look at mx2x.h.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __MACH_MX27_H__
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#define __MACH_MX27_H__
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#ifndef __ASSEMBLER__
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#include <linux/io.h>
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#endif
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#define MX27_AIPI_BASE_ADDR 0x10000000
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#define MX27_AIPI_SIZE SZ_1M
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#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
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#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
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#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
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#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
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#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
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#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
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#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
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#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
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#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
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#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
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#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
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#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
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#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
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#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
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#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
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#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
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#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
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#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
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#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
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#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
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#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
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#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
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#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
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#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
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#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
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#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
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#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
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#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
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#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
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#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
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#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
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#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
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#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
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#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
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#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
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#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
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#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
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#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
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#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
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#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
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#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
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#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
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#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
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#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
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#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
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#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
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#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
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#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
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#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
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#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
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#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
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#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
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#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
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#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
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#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
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#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
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#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
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#define MX27_AVIC_BASE_ADDR 0x10040000
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/* ROM patch */
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#define MX27_ROMP_BASE_ADDR 0x10041000
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#define MX27_SAHB1_BASE_ADDR 0x80000000
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#define MX27_SAHB1_SIZE SZ_1M
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#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
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#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
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/* Memory regions and CS */
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#define MX27_SDRAM_BASE_ADDR 0xa0000000
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#define MX27_CSD1_BASE_ADDR 0xb0000000
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#define MX27_CS0_BASE_ADDR 0xc0000000
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#define MX27_CS1_BASE_ADDR 0xc8000000
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#define MX27_CS2_BASE_ADDR 0xd0000000
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#define MX27_CS3_BASE_ADDR 0xd2000000
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#define MX27_CS4_BASE_ADDR 0xd4000000
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#define MX27_CS5_BASE_ADDR 0xd6000000
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/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
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#define MX27_X_MEMC_BASE_ADDR 0xd8000000
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#define MX27_X_MEMC_SIZE SZ_1M
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#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
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#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
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#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
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#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
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#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
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#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
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#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
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#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
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#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
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#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
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/* IRAM */
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#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
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#define MX27_IO_P2V(x) IMX_IO_P2V(x)
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#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
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#ifndef __ASSEMBLER__
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static inline void mx27_setup_weimcs(size_t cs,
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unsigned upper, unsigned lower, unsigned addional)
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{
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__raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
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__raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
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__raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
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}
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#endif
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/* fixed interrupt numbers */
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#define MX27_INT_I2C2 1
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#define MX27_INT_GPT6 2
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#define MX27_INT_GPT5 3
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#define MX27_INT_GPT4 4
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#define MX27_INT_RTIC 5
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#define MX27_INT_CSPI3 6
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#define MX27_INT_SDHC 7
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#define MX27_INT_GPIO 8
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#define MX27_INT_SDHC3 9
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#define MX27_INT_SDHC2 10
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#define MX27_INT_SDHC1 11
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#define MX27_INT_I2C1 12
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#define MX27_INT_SSI2 13
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#define MX27_INT_SSI1 14
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#define MX27_INT_CSPI2 15
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#define MX27_INT_CSPI1 16
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#define MX27_INT_UART4 17
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#define MX27_INT_UART3 18
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#define MX27_INT_UART2 19
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#define MX27_INT_UART1 20
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#define MX27_INT_KPP 21
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#define MX27_INT_RTC 22
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#define MX27_INT_PWM 23
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#define MX27_INT_GPT3 24
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#define MX27_INT_GPT2 25
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#define MX27_INT_GPT1 26
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#define MX27_INT_WDOG 27
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#define MX27_INT_PCMCIA 28
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#define MX27_INT_NFC 29
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#define MX27_INT_ATA 30
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#define MX27_INT_CSI 31
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#define MX27_INT_DMACH0 32
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#define MX27_INT_DMACH1 33
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#define MX27_INT_DMACH2 34
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#define MX27_INT_DMACH3 35
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#define MX27_INT_DMACH4 36
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#define MX27_INT_DMACH5 37
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#define MX27_INT_DMACH6 38
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#define MX27_INT_DMACH7 39
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#define MX27_INT_DMACH8 40
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#define MX27_INT_DMACH9 41
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#define MX27_INT_DMACH10 42
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#define MX27_INT_DMACH11 43
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#define MX27_INT_DMACH12 44
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#define MX27_INT_DMACH13 45
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#define MX27_INT_DMACH14 46
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#define MX27_INT_DMACH15 47
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#define MX27_INT_UART6 48
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#define MX27_INT_UART5 49
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#define MX27_INT_FEC 50
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#define MX27_INT_EMMAPRP 51
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#define MX27_INT_EMMAPP 52
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#define MX27_INT_VPU 53
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#define MX27_INT_USB_HS1 54
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#define MX27_INT_USB_HS2 55
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#define MX27_INT_USB_OTG 56
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#define MX27_INT_SCC_SMN 57
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#define MX27_INT_SCC_SCM 58
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#define MX27_INT_SAHARA 59
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#define MX27_INT_SLCDC 60
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#define MX27_INT_LCDC 61
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#define MX27_INT_IIM 62
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#define MX27_INT_CCM 63
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/* fixed DMA request numbers */
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#define MX27_DMA_REQ_CSPI3_RX 1
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#define MX27_DMA_REQ_CSPI3_TX 2
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#define MX27_DMA_REQ_EXT 3
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#define MX27_DMA_REQ_MSHC 4
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#define MX27_DMA_REQ_SDHC2 6
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#define MX27_DMA_REQ_SDHC1 7
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#define MX27_DMA_REQ_SSI2_RX0 8
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#define MX27_DMA_REQ_SSI2_TX0 9
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#define MX27_DMA_REQ_SSI2_RX1 10
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#define MX27_DMA_REQ_SSI2_TX1 11
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#define MX27_DMA_REQ_SSI1_RX0 12
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#define MX27_DMA_REQ_SSI1_TX0 13
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#define MX27_DMA_REQ_SSI1_RX1 14
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#define MX27_DMA_REQ_SSI1_TX1 15
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#define MX27_DMA_REQ_CSPI2_RX 16
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#define MX27_DMA_REQ_CSPI2_TX 17
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#define MX27_DMA_REQ_CSPI1_RX 18
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#define MX27_DMA_REQ_CSPI1_TX 19
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#define MX27_DMA_REQ_UART4_RX 20
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#define MX27_DMA_REQ_UART4_TX 21
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#define MX27_DMA_REQ_UART3_RX 22
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#define MX27_DMA_REQ_UART3_TX 23
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#define MX27_DMA_REQ_UART2_RX 24
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#define MX27_DMA_REQ_UART2_TX 25
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#define MX27_DMA_REQ_UART1_RX 26
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#define MX27_DMA_REQ_UART1_TX 27
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#define MX27_DMA_REQ_ATA_TX 28
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#define MX27_DMA_REQ_ATA_RCV 29
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#define MX27_DMA_REQ_CSI_STAT 30
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#define MX27_DMA_REQ_CSI_RX 31
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#define MX27_DMA_REQ_UART5_TX 32
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#define MX27_DMA_REQ_UART5_RX 33
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#define MX27_DMA_REQ_UART6_TX 34
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#define MX27_DMA_REQ_UART6_RX 35
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#define MX27_DMA_REQ_SDHC3 36
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#define MX27_DMA_REQ_NFC 37
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#ifndef __ASSEMBLY__
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extern int mx27_revision(void);
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#endif
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#endif /* ifndef __MACH_MX27_H__ */
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