Jesse Barnes e552eb7038 drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge ... Since 965, the hardware has supported the PIPE_CONTROL command, which provides fine grained GPU cache flushing control. On recent chipsets, this instruction is required for reliable interrupt and sequence number reporting in the driver. So add support for this instruction, including workarounds, on Ironlake and Sandy Bridge hardware. https://bugs.freedesktop.org/show_bug.cgi?id=27108 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Tested-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Eric Anholt <eric@anholt.net>		2010-04-22 14:48:55 -07:00
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drm	drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge	2010-04-22 14:48:55 -07:00
vga	include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h	2010-03-30 22:02:32 +09:00
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