forked from luck/tmp_suning_uos_patched
6ab3d5624e
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de> Signed-off-by: Adrian Bunk <bunk@stusta.de>
157 lines
3.6 KiB
C
157 lines
3.6 KiB
C
/*
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* $Id: l440gx.c,v 1.18 2005/11/07 11:14:27 gleixner Exp $
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*
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* BIOS Flash chip on Intel 440GX board.
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*
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* Bugs this currently does not work under linuxBIOS.
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#define PIIXE_IOBASE_RESOURCE 11
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#define WINDOW_ADDR 0xfff00000
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#define WINDOW_SIZE 0x00100000
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#define BUSWIDTH 1
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static u32 iobase;
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#define IOBASE iobase
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#define TRIBUF_PORT (IOBASE+0x37)
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#define VPP_PORT (IOBASE+0x28)
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static struct mtd_info *mymtd;
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/* Is this really the vpp port? */
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static void l440gx_set_vpp(struct map_info *map, int vpp)
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{
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unsigned long l;
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l = inl(VPP_PORT);
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if (vpp) {
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l |= 1;
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} else {
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l &= ~1;
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}
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outl(l, VPP_PORT);
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}
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static struct map_info l440gx_map = {
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.name = "L440GX BIOS",
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.size = WINDOW_SIZE,
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.bankwidth = BUSWIDTH,
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.phys = WINDOW_ADDR,
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#if 0
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/* FIXME verify that this is the
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* appripriate code for vpp enable/disable
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*/
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.set_vpp = l440gx_set_vpp
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#endif
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};
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static int __init init_l440gx(void)
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{
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struct pci_dev *dev, *pm_dev;
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struct resource *pm_iobase;
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__u16 word;
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dev = pci_find_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB_0, NULL);
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pm_dev = pci_find_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
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if (!dev || !pm_dev) {
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printk(KERN_NOTICE "L440GX flash mapping: failed to find PIIX4 ISA bridge, cannot continue\n");
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return -ENODEV;
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}
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l440gx_map.virt = ioremap_nocache(WINDOW_ADDR, WINDOW_SIZE);
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if (!l440gx_map.virt) {
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printk(KERN_WARNING "Failed to ioremap L440GX flash region\n");
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return -ENOMEM;
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}
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simple_map_init(&l440gx_map);
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printk(KERN_NOTICE "window_addr = 0x%08lx\n", (unsigned long)l440gx_map.virt);
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/* Setup the pm iobase resource
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* This code should move into some kind of generic bridge
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* driver but for the moment I'm content with getting the
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* allocation correct.
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*/
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pm_iobase = &pm_dev->resource[PIIXE_IOBASE_RESOURCE];
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if (!(pm_iobase->flags & IORESOURCE_IO)) {
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pm_iobase->name = "pm iobase";
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pm_iobase->start = 0;
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pm_iobase->end = 63;
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pm_iobase->flags = IORESOURCE_IO;
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/* Put the current value in the resource */
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pci_read_config_dword(pm_dev, 0x40, &iobase);
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iobase &= ~1;
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pm_iobase->start += iobase & ~1;
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pm_iobase->end += iobase & ~1;
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/* Allocate the resource region */
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if (pci_assign_resource(pm_dev, PIIXE_IOBASE_RESOURCE) != 0) {
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printk(KERN_WARNING "Could not allocate pm iobase resource\n");
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iounmap(l440gx_map.virt);
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return -ENXIO;
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}
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}
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/* Set the iobase */
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iobase = pm_iobase->start;
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pci_write_config_dword(pm_dev, 0x40, iobase | 1);
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/* Set XBCS# */
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pci_read_config_word(dev, 0x4e, &word);
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word |= 0x4;
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pci_write_config_word(dev, 0x4e, word);
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/* Supply write voltage to the chip */
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l440gx_set_vpp(&l440gx_map, 1);
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/* Enable the gate on the WE line */
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outb(inb(TRIBUF_PORT) & ~1, TRIBUF_PORT);
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printk(KERN_NOTICE "Enabled WE line to L440GX BIOS flash chip.\n");
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mymtd = do_map_probe("jedec_probe", &l440gx_map);
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if (!mymtd) {
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printk(KERN_NOTICE "JEDEC probe on BIOS chip failed. Using ROM\n");
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mymtd = do_map_probe("map_rom", &l440gx_map);
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}
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if (mymtd) {
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mymtd->owner = THIS_MODULE;
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add_mtd_device(mymtd);
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return 0;
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}
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iounmap(l440gx_map.virt);
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return -ENXIO;
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}
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static void __exit cleanup_l440gx(void)
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{
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del_mtd_device(mymtd);
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map_destroy(mymtd);
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iounmap(l440gx_map.virt);
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}
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module_init(init_l440gx);
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module_exit(cleanup_l440gx);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
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MODULE_DESCRIPTION("MTD map driver for BIOS chips on Intel L440GX motherboards");
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