forked from luck/tmp_suning_uos_patched
f1a0c4aa09
The patch adds functionality required for cache maintenance. The AArch64 architecture mandates non-aliasing VIPT or PIPT D-cache and VIPT (may have aliases) or ASID-tagged VIVT I-cache. Cache maintenance operations are automatically broadcast in hardware between CPUs. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Nicolas Pitre <nico@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
136 lines
3.2 KiB
C
136 lines
3.2 KiB
C
/*
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* Based on arch/arm/mm/flush.c
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*
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* Copyright (C) 1995-2002 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/pagemap.h>
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#include <asm/cacheflush.h>
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#include <asm/cachetype.h>
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#include <asm/tlbflush.h>
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#include "mm.h"
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void flush_cache_mm(struct mm_struct *mm)
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{
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}
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void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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if (vma->vm_flags & VM_EXEC)
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__flush_icache_all();
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}
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void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr,
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unsigned long pfn)
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{
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}
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static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *kaddr,
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unsigned long len)
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{
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if (vma->vm_flags & VM_EXEC) {
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unsigned long addr = (unsigned long)kaddr;
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if (icache_is_aliasing()) {
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__flush_dcache_area(kaddr, len);
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__flush_icache_all();
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} else {
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flush_icache_range(addr, addr + len);
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}
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}
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}
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/*
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* Copy user data from/to a page which is mapped into a different processes
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* address space. Really, we want to allow our "user space" model to handle
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* this.
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*
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* Note that this code needs to run on the current CPU.
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*/
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *dst, const void *src,
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unsigned long len)
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{
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#ifdef CONFIG_SMP
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preempt_disable();
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#endif
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memcpy(dst, src, len);
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flush_ptrace_access(vma, page, uaddr, dst, len);
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#ifdef CONFIG_SMP
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preempt_enable();
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#endif
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}
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void __flush_dcache_page(struct page *page)
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{
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__flush_dcache_area(page_address(page), PAGE_SIZE);
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}
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void __sync_icache_dcache(pte_t pte, unsigned long addr)
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{
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unsigned long pfn;
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struct page *page;
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pfn = pte_pfn(pte);
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if (!pfn_valid(pfn))
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return;
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page = pfn_to_page(pfn);
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if (!test_and_set_bit(PG_dcache_clean, &page->flags)) {
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__flush_dcache_page(page);
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__flush_icache_all();
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} else if (icache_is_aivivt()) {
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__flush_icache_all();
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}
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}
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/*
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* Ensure cache coherency between kernel mapping and userspace mapping of this
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* page.
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*/
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping;
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/*
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* The zero page is never written to, so never has any dirty cache
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* lines, and therefore never needs to be flushed.
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*/
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if (page == ZERO_PAGE(0))
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return;
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mapping = page_mapping(page);
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if (mapping && mapping_mapped(mapping)) {
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__flush_dcache_page(page);
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__flush_icache_all();
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set_bit(PG_dcache_clean, &page->flags);
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} else {
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clear_bit(PG_dcache_clean, &page->flags);
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}
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}
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EXPORT_SYMBOL(flush_dcache_page);
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/*
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* Additional functions defined in assembly.
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*/
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EXPORT_SYMBOL(flush_cache_all);
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EXPORT_SYMBOL(flush_icache_range);
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