forked from luck/tmp_suning_uos_patched
f4151b9ba8
Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/*
|
|
* Modifications by Matt Porter (mporter@mvista.com) to support
|
|
* PPC44x Book E processors.
|
|
*
|
|
* This file contains the routines for initializing the MMU
|
|
* on the 4xx series of chips.
|
|
* -- paulus
|
|
*
|
|
* Derived from arch/ppc/mm/init.c:
|
|
* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
|
|
*
|
|
* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
|
|
* and Cort Dougan (PReP) (cort@cs.nmt.edu)
|
|
* Copyright (C) 1996 Paul Mackerras
|
|
* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
|
|
*
|
|
* Derived from "arch/i386/mm/init.c"
|
|
* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License
|
|
* as published by the Free Software Foundation; either version
|
|
* 2 of the License, or (at your option) any later version.
|
|
*
|
|
*/
|
|
|
|
#include <linux/signal.h>
|
|
#include <linux/sched.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/string.h>
|
|
#include <linux/types.h>
|
|
#include <linux/ptrace.h>
|
|
#include <linux/mman.h>
|
|
#include <linux/mm.h>
|
|
#include <linux/swap.h>
|
|
#include <linux/stddef.h>
|
|
#include <linux/vmalloc.h>
|
|
#include <linux/init.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/highmem.h>
|
|
|
|
#include <asm/pgalloc.h>
|
|
#include <asm/prom.h>
|
|
#include <asm/io.h>
|
|
#include <asm/mmu_context.h>
|
|
#include <asm/pgtable.h>
|
|
#include <asm/mmu.h>
|
|
#include <asm/uaccess.h>
|
|
#include <asm/smp.h>
|
|
#include <asm/bootx.h>
|
|
#include <asm/machdep.h>
|
|
#include <asm/setup.h>
|
|
|
|
#include "mmu_decl.h"
|
|
|
|
extern char etext[], _stext[];
|
|
|
|
/* Used by the 44x TLB replacement exception handler.
|
|
* Just needed it declared someplace.
|
|
*/
|
|
unsigned int tlb_44x_index = 0;
|
|
unsigned int tlb_44x_hwater = PPC4XX_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
|
|
int icache_44x_need_flush;
|
|
|
|
/*
|
|
* "Pins" a 256MB TLB entry in AS0 for kernel lowmem
|
|
*/
|
|
static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
|
|
{
|
|
__asm__ __volatile__(
|
|
"tlbwe %2,%3,%4\n"
|
|
"tlbwe %1,%3,%5\n"
|
|
"tlbwe %0,%3,%6\n"
|
|
:
|
|
: "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
|
|
"r" (phys),
|
|
"r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
|
|
"r" (tlb_44x_hwater--), /* slot for this TLB entry */
|
|
"i" (PPC44x_TLB_PAGEID),
|
|
"i" (PPC44x_TLB_XLAT),
|
|
"i" (PPC44x_TLB_ATTRIB));
|
|
}
|
|
|
|
void __init MMU_init_hw(void)
|
|
{
|
|
flush_instruction_cache();
|
|
}
|
|
|
|
unsigned long __init mmu_mapin_ram(void)
|
|
{
|
|
unsigned long addr;
|
|
|
|
/* Pin in enough TLBs to cover any lowmem not covered by the
|
|
* initial 256M mapping established in head_44x.S */
|
|
for (addr = PPC_PIN_SIZE; addr < total_lowmem;
|
|
addr += PPC_PIN_SIZE)
|
|
ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
|
|
|
|
return total_lowmem;
|
|
}
|