forked from luck/tmp_suning_uos_patched
fd58e55fcf
Abstract portions of the MSI core for platforms that do not use standard APIC interrupt controllers. This is implemented through a new arch-specific msi setup routine, and a set of msi ops which can be set on a per platform basis. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
30 lines
665 B
C
30 lines
665 B
C
/*
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* Copyright (C) 2003-2004 Intel
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* Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
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*/
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#ifndef ASM_MSI_H
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#define ASM_MSI_H
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#define NR_VECTORS NR_IRQS
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#define FIRST_DEVICE_VECTOR IA64_FIRST_DEVICE_VECTOR
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#define LAST_DEVICE_VECTOR IA64_LAST_DEVICE_VECTOR
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static inline void set_intr_gate (int nr, void *func) {}
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#define IO_APIC_VECTOR(irq) (irq)
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#define ack_APIC_irq ia64_eoi
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#define MSI_TARGET_CPU_SHIFT 4
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extern struct msi_ops msi_apic_ops;
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static inline int msi_arch_init(void)
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{
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if (platform_msi_init)
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return platform_msi_init();
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/* default ops for most ia64 platforms */
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msi_register(&msi_apic_ops);
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return 0;
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}
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#endif /* ASM_MSI_H */
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