Dylan Reid ece509c109 ASoC: max98090: Correct pclk divisor settings ... The Baytrail-based chromebooks have a 20MHz mclk, the code was setting the divisor incorrectly in this case. According to the 98090 datasheet, the divisor should be set to DIV1 for 10 <= mclk <= 20. Correct this and the surrounding clock ranges as well to match the datasheet. Signed-off-by: Dylan Reid <dgreid@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>		2014-11-04 19:58:02 +00:00
..
aoa
arm
atmel	dmaengine: dw: split dma-dw.h to platform and private parts	2014-10-15 20:31:04 +05:30
core	ALSA: pcm: Fix referred substream in snd_pcm_action_group() unlock loop	2014-10-14 09:14:48 +02:00
drivers
firewire	ALSA: bebob: Fix failure to detect source of clock for Terratec Phase 88	2014-10-10 17:25:30 +02:00
i2c
isa
mips
oss
parisc
pci	ALSA: hda_intel: Add Device IDs for Intel Sunrise Point PCH	2014-10-15 11:39:58 +02:00
pcmcia
ppc
sh
soc	ASoC: max98090: Correct pclk divisor settings	2014-11-04 19:58:02 +00:00
sparc
spi
synth
usb	sound updates for 3.18-rc1	2014-10-10 22:13:25 -04:00
ac97_bus.c
Kconfig
last.c
Makefile
sound_core.c
sound_firmware.c