forked from luck/tmp_suning_uos_patched
ed4cb4142b
Previous attempts at interrupt mitigation had been foiled by i915_wait_irq's failure to update the sarea seqno value when the status page indicated that the seqno had already been passed. MSI support has been seen to cut CPU costs by up to 40% in some workloads by avoiding other expensive interrupt handlers for frequent graphics interrupts. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Dave Airlie <airlied@redhat.com>
360 lines
11 KiB
C
360 lines
11 KiB
C
/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
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*/
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/*
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*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _I915_DRV_H_
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#define _I915_DRV_H_
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#include "i915_reg.h"
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/* General customization:
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*/
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#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
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#define DRIVER_NAME "i915"
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#define DRIVER_DESC "Intel Graphics"
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#define DRIVER_DATE "20060119"
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/* Interface history:
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*
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* 1.1: Original.
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* 1.2: Add Power Management
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* 1.3: Add vblank support
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* 1.4: Fix cmdbuffer path, add heap destroy
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* 1.5: Add vblank pipe configuration
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* 1.6: - New ioctl for scheduling buffer swaps on vertical blank
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* - Support vertical blank on secondary display pipe
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*/
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 6
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#define DRIVER_PATCHLEVEL 0
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typedef struct _drm_i915_ring_buffer {
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int tail_mask;
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unsigned long Start;
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unsigned long End;
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unsigned long Size;
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u8 *virtual_start;
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int head;
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int tail;
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int space;
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drm_local_map_t map;
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} drm_i915_ring_buffer_t;
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struct mem_block {
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struct mem_block *next;
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struct mem_block *prev;
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int start;
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int size;
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struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
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};
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typedef struct _drm_i915_vbl_swap {
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struct list_head head;
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drm_drawable_t drw_id;
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unsigned int pipe;
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unsigned int sequence;
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} drm_i915_vbl_swap_t;
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typedef struct drm_i915_private {
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drm_local_map_t *sarea;
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drm_local_map_t *mmio_map;
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drm_i915_sarea_t *sarea_priv;
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drm_i915_ring_buffer_t ring;
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drm_dma_handle_t *status_page_dmah;
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void *hw_status_page;
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dma_addr_t dma_status_page;
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unsigned long counter;
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unsigned int status_gfx_addr;
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drm_local_map_t hws_map;
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unsigned int cpp;
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int back_offset;
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int front_offset;
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int current_page;
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int page_flipping;
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wait_queue_head_t irq_queue;
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atomic_t irq_received;
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atomic_t irq_emitted;
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/** Protects user_irq_refcount and irq_mask_reg */
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spinlock_t user_irq_lock;
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/** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
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int user_irq_refcount;
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/** Cached value of IMR to avoid reads in updating the bitfield */
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u32 irq_mask_reg;
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int tex_lru_log_granularity;
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int allow_batchbuffer;
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struct mem_block *agp_heap;
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unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
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int vblank_pipe;
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spinlock_t swaps_lock;
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drm_i915_vbl_swap_t vbl_swaps;
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unsigned int swaps_pending;
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/* Register state */
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u8 saveLBB;
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u32 saveDSPACNTR;
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u32 saveDSPBCNTR;
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u32 saveDSPARB;
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u32 savePIPEACONF;
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u32 savePIPEBCONF;
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u32 savePIPEASRC;
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u32 savePIPEBSRC;
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u32 saveFPA0;
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u32 saveFPA1;
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u32 saveDPLL_A;
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u32 saveDPLL_A_MD;
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u32 saveHTOTAL_A;
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u32 saveHBLANK_A;
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u32 saveHSYNC_A;
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u32 saveVTOTAL_A;
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u32 saveVBLANK_A;
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u32 saveVSYNC_A;
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u32 saveBCLRPAT_A;
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u32 savePIPEASTAT;
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u32 saveDSPASTRIDE;
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u32 saveDSPASIZE;
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u32 saveDSPAPOS;
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u32 saveDSPAADDR;
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u32 saveDSPASURF;
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u32 saveDSPATILEOFF;
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u32 savePFIT_PGM_RATIOS;
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u32 saveBLC_PWM_CTL;
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u32 saveBLC_PWM_CTL2;
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u32 saveFPB0;
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u32 saveFPB1;
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u32 saveDPLL_B;
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u32 saveDPLL_B_MD;
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u32 saveHTOTAL_B;
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u32 saveHBLANK_B;
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u32 saveHSYNC_B;
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u32 saveVTOTAL_B;
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u32 saveVBLANK_B;
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u32 saveVSYNC_B;
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u32 saveBCLRPAT_B;
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u32 savePIPEBSTAT;
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u32 saveDSPBSTRIDE;
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u32 saveDSPBSIZE;
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u32 saveDSPBPOS;
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u32 saveDSPBADDR;
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u32 saveDSPBSURF;
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u32 saveDSPBTILEOFF;
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u32 saveVGA0;
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u32 saveVGA1;
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u32 saveVGA_PD;
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u32 saveVGACNTRL;
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u32 saveADPA;
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u32 saveLVDS;
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u32 savePP_ON_DELAYS;
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u32 savePP_OFF_DELAYS;
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u32 saveDVOA;
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u32 saveDVOB;
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u32 saveDVOC;
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u32 savePP_ON;
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u32 savePP_OFF;
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u32 savePP_CONTROL;
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u32 savePP_DIVISOR;
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u32 savePFIT_CONTROL;
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u32 save_palette_a[256];
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u32 save_palette_b[256];
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u32 saveFBC_CFB_BASE;
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u32 saveFBC_LL_BASE;
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u32 saveFBC_CONTROL;
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u32 saveFBC_CONTROL2;
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u32 saveIER;
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u32 saveIIR;
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u32 saveIMR;
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u32 saveCACHE_MODE_0;
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u32 saveD_STATE;
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u32 saveCG_2D_DIS;
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u32 saveMI_ARB_STATE;
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u32 saveSWF0[16];
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u32 saveSWF1[16];
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u32 saveSWF2[3];
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u8 saveMSR;
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u8 saveSR[8];
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u8 saveGR[25];
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u8 saveAR_INDEX;
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u8 saveAR[21];
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u8 saveDACMASK;
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u8 saveDACDATA[256*3]; /* 256 3-byte colors */
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u8 saveCR[37];
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} drm_i915_private_t;
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extern struct drm_ioctl_desc i915_ioctls[];
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extern int i915_max_ioctl;
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/* i915_dma.c */
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extern void i915_kernel_lost_context(struct drm_device * dev);
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extern int i915_driver_load(struct drm_device *, unsigned long flags);
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extern int i915_driver_unload(struct drm_device *);
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extern void i915_driver_lastclose(struct drm_device * dev);
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extern void i915_driver_preclose(struct drm_device *dev,
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struct drm_file *file_priv);
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extern int i915_driver_device_is_agp(struct drm_device * dev);
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extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
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unsigned long arg);
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/* i915_irq.c */
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extern int i915_irq_emit(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_irq_wait(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence);
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extern int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
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extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
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extern void i915_driver_irq_preinstall(struct drm_device * dev);
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extern void i915_driver_irq_postinstall(struct drm_device * dev);
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extern void i915_driver_irq_uninstall(struct drm_device * dev);
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extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_vblank_swap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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/* i915_mem.c */
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extern int i915_mem_alloc(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_mem_free(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_mem_init_heap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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extern void i915_mem_takedown(struct mem_block **heap);
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extern void i915_mem_release(struct drm_device * dev,
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struct drm_file *file_priv, struct mem_block *heap);
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#define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg))
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#define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val))
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#define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg))
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#define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val))
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#define I915_VERBOSE 0
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#define RING_LOCALS unsigned int outring, ringmask, outcount; \
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volatile char *virt;
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#define BEGIN_LP_RING(n) do { \
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if (I915_VERBOSE) \
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DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
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if (dev_priv->ring.space < (n)*4) \
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i915_wait_ring(dev, (n)*4, __func__); \
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outcount = 0; \
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outring = dev_priv->ring.tail; \
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ringmask = dev_priv->ring.tail_mask; \
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virt = dev_priv->ring.virtual_start; \
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} while (0)
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#define OUT_RING(n) do { \
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if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
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*(volatile unsigned int *)(virt + outring) = (n); \
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outcount++; \
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outring += 4; \
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outring &= ringmask; \
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} while (0)
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#define ADVANCE_LP_RING() do { \
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if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
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dev_priv->ring.tail = outring; \
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dev_priv->ring.space -= outcount * 4; \
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I915_WRITE(PRB0_TAIL, outring); \
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} while(0)
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/**
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* Reads a dword out of the status page, which is written to from the command
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* queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
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* MI_STORE_DATA_IMM.
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*
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* The following dwords have a reserved meaning:
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* 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
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* 4: ring 0 head pointer
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* 5: ring 1 head pointer (915-class)
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* 6: ring 2 head pointer (915-class)
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*
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* The area from dword 0x10 to 0x3ff is available for driver usage.
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*/
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#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
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#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
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extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
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#define IS_I830(dev) ((dev)->pci_device == 0x3577)
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#define IS_845G(dev) ((dev)->pci_device == 0x2562)
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#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
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#define IS_I855(dev) ((dev)->pci_device == 0x3582)
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#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
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#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
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#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
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#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
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#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
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(dev)->pci_device == 0x27AE)
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#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
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(dev)->pci_device == 0x2982 || \
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(dev)->pci_device == 0x2992 || \
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(dev)->pci_device == 0x29A2 || \
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(dev)->pci_device == 0x2A02 || \
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(dev)->pci_device == 0x2A12 || \
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(dev)->pci_device == 0x2A42 || \
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(dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22)
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#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
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#define IS_IGD_GM(dev) ((dev)->pci_device == 0x2A42)
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#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
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(dev)->pci_device == 0x2E12 || \
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(dev)->pci_device == 0x2E22)
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#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
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(dev)->pci_device == 0x29B2 || \
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(dev)->pci_device == 0x29D2)
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#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
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IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
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#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
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IS_I945GM(dev) || IS_I965GM(dev) || IS_IGD_GM(dev))
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#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_IGD_GM(dev) || IS_G4X(dev))
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#define PRIMARY_RINGBUFFER_SIZE (128*1024)
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#endif
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