forked from luck/tmp_suning_uos_patched
1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
182 lines
6.2 KiB
ArmAsm
182 lines
6.2 KiB
ArmAsm
/* $Id: dtlb_backend.S,v 1.16 2001/10/09 04:02:11 davem Exp $
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* dtlb_backend.S: Back end to DTLB miss replacement strategy.
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* This is included directly into the trap table.
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*
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* Copyright (C) 1996,1998 David S. Miller (davem@redhat.com)
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#if PAGE_SHIFT == 13
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#define SZ_BITS _PAGE_SZ8K
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#elif PAGE_SHIFT == 16
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#define SZ_BITS _PAGE_SZ64K
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#elif PAGE_SHIFT == 19
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#define SZ_BITS _PAGE_SZ512K
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#elif PAGE_SHIFT == 22
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#define SZ_BITS _PAGE_SZ4M
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#endif
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#define VALID_SZ_BITS (_PAGE_VALID | SZ_BITS)
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#define VPTE_BITS (_PAGE_CP | _PAGE_CV | _PAGE_P )
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#define VPTE_SHIFT (PAGE_SHIFT - 3)
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/* Ways we can get here:
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*
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* 1) Nucleus loads and stores to/from PA-->VA direct mappings at tl>1.
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* 2) Nucleus loads and stores to/from user/kernel window save areas.
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* 3) VPTE misses from dtlb_base and itlb_base.
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*
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* We need to extract out the PMD and PGDIR indexes from the
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* linear virtual page table access address. The PTE index
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* is at the bottom, but we are not concerned with it. Bits
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* 0 to 2 are clear since each PTE is 8 bytes in size. Each
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* PMD and PGDIR entry are 4 bytes in size. Thus, this
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* address looks something like:
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*
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* |---------------------------------------------------------------|
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* | ... | PGDIR index | PMD index | PTE index | |
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* |---------------------------------------------------------------|
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* 63 F E D C B A 3 2 0 <- bit nr
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*
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* The variable bits above are defined as:
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* A --> 3 + (PAGE_SHIFT - log2(8))
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* --> 3 + (PAGE_SHIFT - 3) - 1
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* (ie. this is "bit 3" + PAGE_SIZE - size of PTE entry in bits - 1)
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* B --> A + 1
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* C --> B + (PAGE_SHIFT - log2(4))
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* --> B + (PAGE_SHIFT - 2) - 1
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* (ie. this is "bit B" + PAGE_SIZE - size of PMD entry in bits - 1)
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* D --> C + 1
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* E --> D + (PAGE_SHIFT - log2(4))
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* --> D + (PAGE_SHIFT - 2) - 1
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* (ie. this is "bit D" + PAGE_SIZE - size of PGDIR entry in bits - 1)
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* F --> E + 1
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*
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* (Note how "B" always evalutes to PAGE_SHIFT, all the other constants
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* cancel out.)
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*
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* For 8K PAGE_SIZE (thus, PAGE_SHIFT of 13) the bit numbers are:
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* A --> 12
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* B --> 13
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* C --> 23
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* D --> 24
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* E --> 34
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* F --> 35
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*
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* For 64K PAGE_SIZE (thus, PAGE_SHIFT of 16) the bit numbers are:
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* A --> 15
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* B --> 16
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* C --> 29
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* D --> 30
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* E --> 43
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* F --> 44
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*
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* Because bits both above and below each PGDIR and PMD index need to
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* be masked out, and the index can be as long as 14 bits (when using a
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* 64K PAGE_SIZE, and thus a PAGE_SHIFT of 16), we need 3 instructions
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* to extract each index out.
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*
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* Shifts do not pair very well on UltraSPARC-I, II, IIi, and IIe, so
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* we try to avoid using them for the entire operation. We could setup
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* a mask anywhere from bit 31 down to bit 10 using the sethi instruction.
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*
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* We need a mask covering bits B --> C and one covering D --> E.
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* For 8K PAGE_SIZE these masks are 0x00ffe000 and 0x7ff000000.
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* For 64K PAGE_SIZE these masks are 0x3fff0000 and 0xfffc0000000.
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* The second in each set cannot be loaded with a single sethi
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* instruction, because the upper bits are past bit 32. We would
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* need to use a sethi + a shift.
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*
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* For the time being, we use 2 shifts and a simple "and" mask.
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* We shift left to clear the bits above the index, we shift down
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* to clear the bits below the index (sans the log2(4 or 8) bits)
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* and a mask to clear the log2(4 or 8) bits. We need therefore
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* define 4 shift counts, all of which are relative to PAGE_SHIFT.
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*
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* Although unsupportable for other reasons, this does mean that
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* 512K and 4MB page sizes would be generaally supported by the
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* kernel. (ELF binaries would break with > 64K PAGE_SIZE since
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* the sections are only aligned that strongly).
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*
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* The operations performed for extraction are thus:
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*
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* ((X << FOO_SHIFT_LEFT) >> FOO_SHIFT_RIGHT) & ~0x3
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*
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*/
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#define A (3 + (PAGE_SHIFT - 3) - 1)
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#define B (A + 1)
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#define C (B + (PAGE_SHIFT - 2) - 1)
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#define D (C + 1)
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#define E (D + (PAGE_SHIFT - 2) - 1)
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#define F (E + 1)
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#define PMD_SHIFT_LEFT (64 - D)
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#define PMD_SHIFT_RIGHT (64 - (D - B) - 2)
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#define PGDIR_SHIFT_LEFT (64 - F)
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#define PGDIR_SHIFT_RIGHT (64 - (F - D) - 2)
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#define LOW_MASK_BITS 0x3
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/* TLB1 ** ICACHE line 1: tl1 DTLB and quick VPTE miss */
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ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS
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add %g3, %g3, %g5 ! Compute VPTE base
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cmp %g4, %g5 ! VPTE miss?
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bgeu,pt %xcc, 1f ! Continue here
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andcc %g4, TAG_CONTEXT_BITS, %g5 ! tl0 miss Nucleus test
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ba,a,pt %xcc, from_tl1_trap ! Fall to tl0 miss
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1: sllx %g6, VPTE_SHIFT, %g4 ! Position TAG_ACCESS
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or %g4, %g5, %g4 ! Prepare TAG_ACCESS
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/* TLB1 ** ICACHE line 2: Quick VPTE miss */
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mov TSB_REG, %g1 ! Grab TSB reg
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ldxa [%g1] ASI_DMMU, %g5 ! Doing PGD caching?
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sllx %g6, PMD_SHIFT_LEFT, %g1 ! Position PMD offset
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be,pn %xcc, sparc64_vpte_nucleus ! Is it from Nucleus?
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srlx %g1, PMD_SHIFT_RIGHT, %g1 ! Mask PMD offset bits
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brnz,pt %g5, sparc64_vpte_continue ! Yep, go like smoke
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andn %g1, LOW_MASK_BITS, %g1 ! Final PMD mask
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sllx %g6, PGDIR_SHIFT_LEFT, %g5 ! Position PGD offset
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/* TLB1 ** ICACHE line 3: Quick VPTE miss */
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srlx %g5, PGDIR_SHIFT_RIGHT, %g5 ! Mask PGD offset bits
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andn %g5, LOW_MASK_BITS, %g5 ! Final PGD mask
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lduwa [%g7 + %g5] ASI_PHYS_USE_EC, %g5! Load PGD
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brz,pn %g5, vpte_noent ! Valid?
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sparc64_kpte_continue:
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sllx %g5, 11, %g5 ! Shift into place
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sparc64_vpte_continue:
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lduwa [%g5 + %g1] ASI_PHYS_USE_EC, %g5! Load PMD
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sllx %g5, 11, %g5 ! Shift into place
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brz,pn %g5, vpte_noent ! Valid?
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/* TLB1 ** ICACHE line 4: Quick VPTE miss */
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mov (VALID_SZ_BITS >> 61), %g1 ! upper vpte into %g1
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sllx %g1, 61, %g1 ! finish calc
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or %g5, VPTE_BITS, %g5 ! Prepare VPTE data
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or %g5, %g1, %g5 ! ...
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mov TLB_SFSR, %g1 ! Restore %g1 value
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stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Load VPTE into TLB
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stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS
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retry ! Load PTE once again
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#undef SZ_BITS
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#undef VALID_SZ_BITS
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#undef VPTE_SHIFT
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#undef VPTE_BITS
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#undef A
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#undef B
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#undef C
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#undef D
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#undef E
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#undef F
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#undef PMD_SHIFT_LEFT
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#undef PMD_SHIFT_RIGHT
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#undef PGDIR_SHIFT_LEFT
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#undef PGDIR_SHIFT_RIGHT
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#undef LOW_MASK_BITS
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