forked from luck/tmp_suning_uos_patched
f0ed4e695f
On Sat, Sep 06, 2008 at 06:03:53AM -0700, Ingo Molnar wrote: > > it crashes two testsystems, the fault on a NULL pointer in hpet init, > with: > > initcall print_all_ICs+0x0/0x520 returned 0 after 26 msecs > calling hpet_late_init+0x0/0x1c0 > BUG: unable to handle kernel NULL pointer dereference at 000000000000008c > IP: [<ffffffff80d228be>] hpet_late_init+0xfe/0x1c0 > PGD 0 > Oops: 0000 [1] SMP > CPU 0 > Modules linked in: > Pid: 1, comm: swapper Not tainted 2.6.27-rc5 #29725 > RIP: 0010:[<ffffffff80d228be>] [<ffffffff80d228be>] hpet_late_init+0xfe/0x1c0 > RSP: 0018:ffff88003fa07dd0 EFLAGS: 00010246 > RAX: 0000000000000000 RBX: 0000000000000003 RCX: 0000000000000000 > RDX: ffffc20000000160 RSI: 0000000000000000 RDI: 0000000000000003 > RBP: ffff88003fa07e90 R08: 0000000000000000 R09: ffff88003fa07dd0 > R10: 0000000000000001 R11: 0000000000000000 R12: ffff88003fa07dd0 > R13: 0000000000000002 R14: ffffc20000000000 R15: 000000006f57e511 > FS: 0000000000000000(0000) GS:ffffffff80cf6a80(0000) knlGS:0000000000000000 > CS: 0010 DS: 0018 ES: 0018 CR0: 000000008005003b > CR2: 000000000000008c CR3: 0000000000201000 CR4: 00000000000006e0 > DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 > DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 > Process swapper (pid: 1, threadinfo ffff88003fa06000, task ffff88003fa08000) > Stack: 00000000fed00000 ffffc20000000000 0000000100000003 0000000800000002 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > Call Trace: > [<ffffffff80d227c0>] ? hpet_late_init+0x0/0x1c0 > [<ffffffff80209045>] do_one_initcall+0x45/0x190 > [<ffffffff80296f39>] ? register_irq_proc+0x19/0xe0 > [<ffffffff80d0d140>] ? early_idt_handler+0x0/0x73 > [<ffffffff80d0dabc>] kernel_init+0x14c/0x1b0 > [<ffffffff80942ac1>] ? trace_hardirqs_on_thunk+0x3a/0x3f > [<ffffffff8020dbd9>] child_rip+0xa/0x11 > [<ffffffff8020ceee>] ? restore_args+0x0/0x30 > [<ffffffff80d0d970>] ? kernel_init+0x0/0x1b0 > [<ffffffff8020dbcf>] ? child_rip+0x0/0x11 > Code: 20 48 83 c1 01 48 39 f1 75 e3 44 89 e8 4c 8b 05 29 29 22 00 31 f6 48 8d 78 01 66 66 90 89 f0 48 8d 04 80 48 c1 e0 05 4a 8d 0c 00 <f6> 81 8c 00 00 00 08 74 26 8b 81 80 00 00 00 8b 91 88 00 00 00 > RIP [<ffffffff80d228be>] hpet_late_init+0xfe/0x1c0 > RSP <ffff88003fa07dd0> > CR2: 000000000000008c > Kernel panic - not syncing: Fatal exception There was one code path, with CONFIG_PCI_MSI disabled, where we were accessing hpet_devs without initialization. That resulted in the above crash. The change below adds a check for hpet_devs. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
1104 lines
25 KiB
C
1104 lines
25 KiB
C
#include <linux/clocksource.h>
|
|
#include <linux/clockchips.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/sysdev.h>
|
|
#include <linux/delay.h>
|
|
#include <linux/errno.h>
|
|
#include <linux/hpet.h>
|
|
#include <linux/init.h>
|
|
#include <linux/cpu.h>
|
|
#include <linux/pm.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <asm/fixmap.h>
|
|
#include <asm/i8253.h>
|
|
#include <asm/hpet.h>
|
|
|
|
#define HPET_MASK CLOCKSOURCE_MASK(32)
|
|
#define HPET_SHIFT 22
|
|
|
|
/* FSEC = 10^-15
|
|
NSEC = 10^-9 */
|
|
#define FSEC_PER_NSEC 1000000L
|
|
|
|
#define HPET_DEV_USED_BIT 2
|
|
#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
|
|
#define HPET_DEV_VALID 0x8
|
|
#define HPET_DEV_FSB_CAP 0x1000
|
|
#define HPET_DEV_PERI_CAP 0x2000
|
|
|
|
#define EVT_TO_HPET_DEV(evt) container_of(evt, struct hpet_dev, evt)
|
|
|
|
/*
|
|
* HPET address is set in acpi/boot.c, when an ACPI entry exists
|
|
*/
|
|
unsigned long hpet_address;
|
|
unsigned long hpet_num_timers;
|
|
static void __iomem *hpet_virt_address;
|
|
|
|
struct hpet_dev {
|
|
struct clock_event_device evt;
|
|
unsigned int num;
|
|
int cpu;
|
|
unsigned int irq;
|
|
unsigned int flags;
|
|
char name[10];
|
|
};
|
|
|
|
static struct hpet_dev *hpet_devs;
|
|
|
|
static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
|
|
|
|
unsigned long hpet_readl(unsigned long a)
|
|
{
|
|
return readl(hpet_virt_address + a);
|
|
}
|
|
|
|
static inline void hpet_writel(unsigned long d, unsigned long a)
|
|
{
|
|
writel(d, hpet_virt_address + a);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
#include <asm/pgtable.h>
|
|
#endif
|
|
|
|
static inline void hpet_set_mapping(void)
|
|
{
|
|
hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
|
|
#ifdef CONFIG_X86_64
|
|
__set_fixmap(VSYSCALL_HPET, hpet_address, PAGE_KERNEL_VSYSCALL_NOCACHE);
|
|
#endif
|
|
}
|
|
|
|
static inline void hpet_clear_mapping(void)
|
|
{
|
|
iounmap(hpet_virt_address);
|
|
hpet_virt_address = NULL;
|
|
}
|
|
|
|
/*
|
|
* HPET command line enable / disable
|
|
*/
|
|
static int boot_hpet_disable;
|
|
int hpet_force_user;
|
|
|
|
static int __init hpet_setup(char *str)
|
|
{
|
|
if (str) {
|
|
if (!strncmp("disable", str, 7))
|
|
boot_hpet_disable = 1;
|
|
if (!strncmp("force", str, 5))
|
|
hpet_force_user = 1;
|
|
}
|
|
return 1;
|
|
}
|
|
__setup("hpet=", hpet_setup);
|
|
|
|
static int __init disable_hpet(char *str)
|
|
{
|
|
boot_hpet_disable = 1;
|
|
return 1;
|
|
}
|
|
__setup("nohpet", disable_hpet);
|
|
|
|
static inline int is_hpet_capable(void)
|
|
{
|
|
return !boot_hpet_disable && hpet_address;
|
|
}
|
|
|
|
/*
|
|
* HPET timer interrupt enable / disable
|
|
*/
|
|
static int hpet_legacy_int_enabled;
|
|
|
|
/**
|
|
* is_hpet_enabled - check whether the hpet timer interrupt is enabled
|
|
*/
|
|
int is_hpet_enabled(void)
|
|
{
|
|
return is_hpet_capable() && hpet_legacy_int_enabled;
|
|
}
|
|
EXPORT_SYMBOL_GPL(is_hpet_enabled);
|
|
|
|
/*
|
|
* When the hpet driver (/dev/hpet) is enabled, we need to reserve
|
|
* timer 0 and timer 1 in case of RTC emulation.
|
|
*/
|
|
#ifdef CONFIG_HPET
|
|
static void hpet_reserve_msi_timers(struct hpet_data *hd)
|
|
{
|
|
int i;
|
|
|
|
if (!hpet_devs)
|
|
return;
|
|
|
|
for (i = 0; i < hpet_num_timers; i++) {
|
|
struct hpet_dev *hdev = &hpet_devs[i];
|
|
|
|
if (!(hdev->flags & HPET_DEV_VALID))
|
|
continue;
|
|
|
|
hd->hd_irq[hdev->num] = hdev->irq;
|
|
hpet_reserve_timer(hd, hdev->num);
|
|
}
|
|
}
|
|
|
|
static void hpet_reserve_platform_timers(unsigned long id)
|
|
{
|
|
struct hpet __iomem *hpet = hpet_virt_address;
|
|
struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
|
|
unsigned int nrtimers, i;
|
|
struct hpet_data hd;
|
|
|
|
nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
|
|
|
|
memset(&hd, 0, sizeof(hd));
|
|
hd.hd_phys_address = hpet_address;
|
|
hd.hd_address = hpet;
|
|
hd.hd_nirqs = nrtimers;
|
|
hpet_reserve_timer(&hd, 0);
|
|
|
|
#ifdef CONFIG_HPET_EMULATE_RTC
|
|
hpet_reserve_timer(&hd, 1);
|
|
#endif
|
|
|
|
/*
|
|
* NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
|
|
* is wrong for i8259!) not the output IRQ. Many BIOS writers
|
|
* don't bother configuring *any* comparator interrupts.
|
|
*/
|
|
hd.hd_irq[0] = HPET_LEGACY_8254;
|
|
hd.hd_irq[1] = HPET_LEGACY_RTC;
|
|
|
|
for (i = 2; i < nrtimers; timer++, i++) {
|
|
hd.hd_irq[i] = (readl(&timer->hpet_config) &
|
|
Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
|
|
}
|
|
|
|
hpet_reserve_msi_timers(&hd);
|
|
|
|
hpet_alloc(&hd);
|
|
|
|
}
|
|
#else
|
|
static void hpet_reserve_platform_timers(unsigned long id) { }
|
|
#endif
|
|
|
|
/*
|
|
* Common hpet info
|
|
*/
|
|
static unsigned long hpet_period;
|
|
|
|
static void hpet_legacy_set_mode(enum clock_event_mode mode,
|
|
struct clock_event_device *evt);
|
|
static int hpet_legacy_next_event(unsigned long delta,
|
|
struct clock_event_device *evt);
|
|
|
|
/*
|
|
* The hpet clock event device
|
|
*/
|
|
static struct clock_event_device hpet_clockevent = {
|
|
.name = "hpet",
|
|
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
|
.set_mode = hpet_legacy_set_mode,
|
|
.set_next_event = hpet_legacy_next_event,
|
|
.shift = 32,
|
|
.irq = 0,
|
|
.rating = 50,
|
|
};
|
|
|
|
static void hpet_start_counter(void)
|
|
{
|
|
unsigned long cfg = hpet_readl(HPET_CFG);
|
|
|
|
cfg &= ~HPET_CFG_ENABLE;
|
|
hpet_writel(cfg, HPET_CFG);
|
|
hpet_writel(0, HPET_COUNTER);
|
|
hpet_writel(0, HPET_COUNTER + 4);
|
|
cfg |= HPET_CFG_ENABLE;
|
|
hpet_writel(cfg, HPET_CFG);
|
|
}
|
|
|
|
static void hpet_resume_device(void)
|
|
{
|
|
force_hpet_resume();
|
|
}
|
|
|
|
static void hpet_restart_counter(void)
|
|
{
|
|
hpet_resume_device();
|
|
hpet_start_counter();
|
|
}
|
|
|
|
static void hpet_enable_legacy_int(void)
|
|
{
|
|
unsigned long cfg = hpet_readl(HPET_CFG);
|
|
|
|
cfg |= HPET_CFG_LEGACY;
|
|
hpet_writel(cfg, HPET_CFG);
|
|
hpet_legacy_int_enabled = 1;
|
|
}
|
|
|
|
static void hpet_legacy_clockevent_register(void)
|
|
{
|
|
/* Start HPET legacy interrupts */
|
|
hpet_enable_legacy_int();
|
|
|
|
/*
|
|
* The mult factor is defined as (include/linux/clockchips.h)
|
|
* mult/2^shift = cyc/ns (in contrast to ns/cyc in clocksource.h)
|
|
* hpet_period is in units of femtoseconds (per cycle), so
|
|
* mult/2^shift = cyc/ns = 10^6/hpet_period
|
|
* mult = (10^6 * 2^shift)/hpet_period
|
|
* mult = (FSEC_PER_NSEC << hpet_clockevent.shift)/hpet_period
|
|
*/
|
|
hpet_clockevent.mult = div_sc((unsigned long) FSEC_PER_NSEC,
|
|
hpet_period, hpet_clockevent.shift);
|
|
/* Calculate the min / max delta */
|
|
hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
|
|
&hpet_clockevent);
|
|
/* 5 usec minimum reprogramming delta. */
|
|
hpet_clockevent.min_delta_ns = 5000;
|
|
|
|
/*
|
|
* Start hpet with the boot cpu mask and make it
|
|
* global after the IO_APIC has been initialized.
|
|
*/
|
|
hpet_clockevent.cpumask = cpumask_of_cpu(smp_processor_id());
|
|
clockevents_register_device(&hpet_clockevent);
|
|
global_clock_event = &hpet_clockevent;
|
|
printk(KERN_DEBUG "hpet clockevent registered\n");
|
|
}
|
|
|
|
static int hpet_setup_msi_irq(unsigned int irq);
|
|
|
|
static void hpet_set_mode(enum clock_event_mode mode,
|
|
struct clock_event_device *evt, int timer)
|
|
{
|
|
unsigned long cfg, cmp, now;
|
|
uint64_t delta;
|
|
|
|
switch (mode) {
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
|
delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
|
|
delta >>= evt->shift;
|
|
now = hpet_readl(HPET_COUNTER);
|
|
cmp = now + (unsigned long) delta;
|
|
cfg = hpet_readl(HPET_Tn_CFG(timer));
|
|
cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
|
|
HPET_TN_SETVAL | HPET_TN_32BIT;
|
|
hpet_writel(cfg, HPET_Tn_CFG(timer));
|
|
/*
|
|
* The first write after writing TN_SETVAL to the
|
|
* config register sets the counter value, the second
|
|
* write sets the period.
|
|
*/
|
|
hpet_writel(cmp, HPET_Tn_CMP(timer));
|
|
udelay(1);
|
|
hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_ONESHOT:
|
|
cfg = hpet_readl(HPET_Tn_CFG(timer));
|
|
cfg &= ~HPET_TN_PERIODIC;
|
|
cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
|
|
hpet_writel(cfg, HPET_Tn_CFG(timer));
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
cfg = hpet_readl(HPET_Tn_CFG(timer));
|
|
cfg &= ~HPET_TN_ENABLE;
|
|
hpet_writel(cfg, HPET_Tn_CFG(timer));
|
|
break;
|
|
|
|
case CLOCK_EVT_MODE_RESUME:
|
|
if (timer == 0) {
|
|
hpet_enable_legacy_int();
|
|
} else {
|
|
struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
|
|
hpet_setup_msi_irq(hdev->irq);
|
|
disable_irq(hdev->irq);
|
|
irq_set_affinity(hdev->irq, cpumask_of_cpu(hdev->cpu));
|
|
enable_irq(hdev->irq);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int hpet_next_event(unsigned long delta,
|
|
struct clock_event_device *evt, int timer)
|
|
{
|
|
u32 cnt;
|
|
|
|
cnt = hpet_readl(HPET_COUNTER);
|
|
cnt += (u32) delta;
|
|
hpet_writel(cnt, HPET_Tn_CMP(timer));
|
|
|
|
/*
|
|
* We need to read back the CMP register to make sure that
|
|
* what we wrote hit the chip before we compare it to the
|
|
* counter.
|
|
*/
|
|
WARN_ON((u32)hpet_readl(HPET_T0_CMP) != cnt);
|
|
|
|
return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
|
|
}
|
|
|
|
static void hpet_legacy_set_mode(enum clock_event_mode mode,
|
|
struct clock_event_device *evt)
|
|
{
|
|
hpet_set_mode(mode, evt, 0);
|
|
}
|
|
|
|
static int hpet_legacy_next_event(unsigned long delta,
|
|
struct clock_event_device *evt)
|
|
{
|
|
return hpet_next_event(delta, evt, 0);
|
|
}
|
|
|
|
/*
|
|
* HPET MSI Support
|
|
*/
|
|
#ifdef CONFIG_PCI_MSI
|
|
void hpet_msi_unmask(unsigned int irq)
|
|
{
|
|
struct hpet_dev *hdev = get_irq_data(irq);
|
|
unsigned long cfg;
|
|
|
|
/* unmask it */
|
|
cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
|
|
cfg |= HPET_TN_FSB;
|
|
hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
|
|
}
|
|
|
|
void hpet_msi_mask(unsigned int irq)
|
|
{
|
|
unsigned long cfg;
|
|
struct hpet_dev *hdev = get_irq_data(irq);
|
|
|
|
/* mask it */
|
|
cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
|
|
cfg &= ~HPET_TN_FSB;
|
|
hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
|
|
}
|
|
|
|
void hpet_msi_write(unsigned int irq, struct msi_msg *msg)
|
|
{
|
|
struct hpet_dev *hdev = get_irq_data(irq);
|
|
|
|
hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
|
|
hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
|
|
}
|
|
|
|
void hpet_msi_read(unsigned int irq, struct msi_msg *msg)
|
|
{
|
|
struct hpet_dev *hdev = get_irq_data(irq);
|
|
|
|
msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
|
|
msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
|
|
msg->address_hi = 0;
|
|
}
|
|
|
|
static void hpet_msi_set_mode(enum clock_event_mode mode,
|
|
struct clock_event_device *evt)
|
|
{
|
|
struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
|
|
hpet_set_mode(mode, evt, hdev->num);
|
|
}
|
|
|
|
static int hpet_msi_next_event(unsigned long delta,
|
|
struct clock_event_device *evt)
|
|
{
|
|
struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
|
|
return hpet_next_event(delta, evt, hdev->num);
|
|
}
|
|
|
|
static int hpet_setup_msi_irq(unsigned int irq)
|
|
{
|
|
if (arch_setup_hpet_msi(irq)) {
|
|
destroy_irq(irq);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int hpet_assign_irq(struct hpet_dev *dev)
|
|
{
|
|
unsigned int irq;
|
|
|
|
irq = create_irq();
|
|
if (!irq)
|
|
return -EINVAL;
|
|
|
|
set_irq_data(irq, dev);
|
|
|
|
if (hpet_setup_msi_irq(irq))
|
|
return -EINVAL;
|
|
|
|
dev->irq = irq;
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t hpet_interrupt_handler(int irq, void *data)
|
|
{
|
|
struct hpet_dev *dev = (struct hpet_dev *)data;
|
|
struct clock_event_device *hevt = &dev->evt;
|
|
|
|
if (!hevt->event_handler) {
|
|
printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
|
|
dev->num);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
hevt->event_handler(hevt);
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int hpet_setup_irq(struct hpet_dev *dev)
|
|
{
|
|
|
|
if (request_irq(dev->irq, hpet_interrupt_handler,
|
|
IRQF_SHARED|IRQF_NOBALANCING, dev->name, dev))
|
|
return -1;
|
|
|
|
disable_irq(dev->irq);
|
|
irq_set_affinity(dev->irq, cpumask_of_cpu(dev->cpu));
|
|
enable_irq(dev->irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* This should be called in specific @cpu */
|
|
static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
|
|
{
|
|
struct clock_event_device *evt = &hdev->evt;
|
|
uint64_t hpet_freq;
|
|
|
|
WARN_ON(cpu != smp_processor_id());
|
|
if (!(hdev->flags & HPET_DEV_VALID))
|
|
return;
|
|
|
|
if (hpet_setup_msi_irq(hdev->irq))
|
|
return;
|
|
|
|
hdev->cpu = cpu;
|
|
per_cpu(cpu_hpet_dev, cpu) = hdev;
|
|
evt->name = hdev->name;
|
|
hpet_setup_irq(hdev);
|
|
evt->irq = hdev->irq;
|
|
|
|
evt->rating = 110;
|
|
evt->features = CLOCK_EVT_FEAT_ONESHOT;
|
|
if (hdev->flags & HPET_DEV_PERI_CAP)
|
|
evt->features |= CLOCK_EVT_FEAT_PERIODIC;
|
|
|
|
evt->set_mode = hpet_msi_set_mode;
|
|
evt->set_next_event = hpet_msi_next_event;
|
|
evt->shift = 32;
|
|
|
|
/*
|
|
* The period is a femto seconds value. We need to calculate the
|
|
* scaled math multiplication factor for nanosecond to hpet tick
|
|
* conversion.
|
|
*/
|
|
hpet_freq = 1000000000000000ULL;
|
|
do_div(hpet_freq, hpet_period);
|
|
evt->mult = div_sc((unsigned long) hpet_freq,
|
|
NSEC_PER_SEC, evt->shift);
|
|
/* Calculate the max delta */
|
|
evt->max_delta_ns = clockevent_delta2ns(0x7FFFFFFF, evt);
|
|
/* 5 usec minimum reprogramming delta. */
|
|
evt->min_delta_ns = 5000;
|
|
|
|
evt->cpumask = cpumask_of_cpu(hdev->cpu);
|
|
clockevents_register_device(evt);
|
|
}
|
|
|
|
#ifdef CONFIG_HPET
|
|
/* Reserve at least one timer for userspace (/dev/hpet) */
|
|
#define RESERVE_TIMERS 1
|
|
#else
|
|
#define RESERVE_TIMERS 0
|
|
#endif
|
|
void hpet_msi_capability_lookup(unsigned int start_timer)
|
|
{
|
|
unsigned int id;
|
|
unsigned int num_timers;
|
|
unsigned int num_timers_used = 0;
|
|
int i;
|
|
|
|
id = hpet_readl(HPET_ID);
|
|
|
|
num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
|
|
num_timers++; /* Value read out starts from 0 */
|
|
|
|
hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
|
|
if (!hpet_devs)
|
|
return;
|
|
|
|
hpet_num_timers = num_timers;
|
|
|
|
for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
|
|
struct hpet_dev *hdev = &hpet_devs[num_timers_used];
|
|
unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
|
|
|
|
/* Only consider HPET timer with MSI support */
|
|
if (!(cfg & HPET_TN_FSB_CAP))
|
|
continue;
|
|
|
|
hdev->flags = 0;
|
|
if (cfg & HPET_TN_PERIODIC_CAP)
|
|
hdev->flags |= HPET_DEV_PERI_CAP;
|
|
hdev->num = i;
|
|
|
|
sprintf(hdev->name, "hpet%d", i);
|
|
if (hpet_assign_irq(hdev))
|
|
continue;
|
|
|
|
hdev->flags |= HPET_DEV_FSB_CAP;
|
|
hdev->flags |= HPET_DEV_VALID;
|
|
num_timers_used++;
|
|
if (num_timers_used == num_possible_cpus())
|
|
break;
|
|
}
|
|
|
|
printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
|
|
num_timers, num_timers_used);
|
|
}
|
|
|
|
static struct hpet_dev *hpet_get_unused_timer(void)
|
|
{
|
|
int i;
|
|
|
|
if (!hpet_devs)
|
|
return NULL;
|
|
|
|
for (i = 0; i < hpet_num_timers; i++) {
|
|
struct hpet_dev *hdev = &hpet_devs[i];
|
|
|
|
if (!(hdev->flags & HPET_DEV_VALID))
|
|
continue;
|
|
if (test_and_set_bit(HPET_DEV_USED_BIT,
|
|
(unsigned long *)&hdev->flags))
|
|
continue;
|
|
return hdev;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
struct hpet_work_struct {
|
|
struct delayed_work work;
|
|
struct completion complete;
|
|
};
|
|
|
|
static void hpet_work(struct work_struct *w)
|
|
{
|
|
struct hpet_dev *hdev;
|
|
int cpu = smp_processor_id();
|
|
struct hpet_work_struct *hpet_work;
|
|
|
|
hpet_work = container_of(w, struct hpet_work_struct, work.work);
|
|
|
|
hdev = hpet_get_unused_timer();
|
|
if (hdev)
|
|
init_one_hpet_msi_clockevent(hdev, cpu);
|
|
|
|
complete(&hpet_work->complete);
|
|
}
|
|
|
|
static int hpet_cpuhp_notify(struct notifier_block *n,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
unsigned long cpu = (unsigned long)hcpu;
|
|
struct hpet_work_struct work;
|
|
struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
|
|
|
|
switch (action & 0xf) {
|
|
case CPU_ONLINE:
|
|
INIT_DELAYED_WORK(&work.work, hpet_work);
|
|
init_completion(&work.complete);
|
|
/* FIXME: add schedule_work_on() */
|
|
schedule_delayed_work_on(cpu, &work.work, 0);
|
|
wait_for_completion(&work.complete);
|
|
break;
|
|
case CPU_DEAD:
|
|
if (hdev) {
|
|
free_irq(hdev->irq, hdev);
|
|
hdev->flags &= ~HPET_DEV_USED;
|
|
per_cpu(cpu_hpet_dev, cpu) = NULL;
|
|
}
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
#else
|
|
|
|
void hpet_msi_capability_lookup(unsigned int start_timer)
|
|
{
|
|
return;
|
|
}
|
|
|
|
static int hpet_cpuhp_notify(struct notifier_block *n,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Clock source related code
|
|
*/
|
|
static cycle_t read_hpet(void)
|
|
{
|
|
return (cycle_t)hpet_readl(HPET_COUNTER);
|
|
}
|
|
|
|
#ifdef CONFIG_X86_64
|
|
static cycle_t __vsyscall_fn vread_hpet(void)
|
|
{
|
|
return readl((const void __iomem *)fix_to_virt(VSYSCALL_HPET) + 0xf0);
|
|
}
|
|
#endif
|
|
|
|
static struct clocksource clocksource_hpet = {
|
|
.name = "hpet",
|
|
.rating = 250,
|
|
.read = read_hpet,
|
|
.mask = HPET_MASK,
|
|
.shift = HPET_SHIFT,
|
|
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
|
.resume = hpet_restart_counter,
|
|
#ifdef CONFIG_X86_64
|
|
.vread = vread_hpet,
|
|
#endif
|
|
};
|
|
|
|
static int hpet_clocksource_register(void)
|
|
{
|
|
u64 start, now;
|
|
cycle_t t1;
|
|
|
|
/* Start the counter */
|
|
hpet_start_counter();
|
|
|
|
/* Verify whether hpet counter works */
|
|
t1 = read_hpet();
|
|
rdtscll(start);
|
|
|
|
/*
|
|
* We don't know the TSC frequency yet, but waiting for
|
|
* 200000 TSC cycles is safe:
|
|
* 4 GHz == 50us
|
|
* 1 GHz == 200us
|
|
*/
|
|
do {
|
|
rep_nop();
|
|
rdtscll(now);
|
|
} while ((now - start) < 200000UL);
|
|
|
|
if (t1 == read_hpet()) {
|
|
printk(KERN_WARNING
|
|
"HPET counter not counting. HPET disabled\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* The definition of mult is (include/linux/clocksource.h)
|
|
* mult/2^shift = ns/cyc and hpet_period is in units of fsec/cyc
|
|
* so we first need to convert hpet_period to ns/cyc units:
|
|
* mult/2^shift = ns/cyc = hpet_period/10^6
|
|
* mult = (hpet_period * 2^shift)/10^6
|
|
* mult = (hpet_period << shift)/FSEC_PER_NSEC
|
|
*/
|
|
clocksource_hpet.mult = div_sc(hpet_period, FSEC_PER_NSEC, HPET_SHIFT);
|
|
|
|
clocksource_register(&clocksource_hpet);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* hpet_enable - Try to setup the HPET timer. Returns 1 on success.
|
|
*/
|
|
int __init hpet_enable(void)
|
|
{
|
|
unsigned long id;
|
|
int i;
|
|
|
|
if (!is_hpet_capable())
|
|
return 0;
|
|
|
|
hpet_set_mapping();
|
|
|
|
/*
|
|
* Read the period and check for a sane value:
|
|
*/
|
|
hpet_period = hpet_readl(HPET_PERIOD);
|
|
|
|
/*
|
|
* AMD SB700 based systems with spread spectrum enabled use a
|
|
* SMM based HPET emulation to provide proper frequency
|
|
* setting. The SMM code is initialized with the first HPET
|
|
* register access and takes some time to complete. During
|
|
* this time the config register reads 0xffffffff. We check
|
|
* for max. 1000 loops whether the config register reads a non
|
|
* 0xffffffff value to make sure that HPET is up and running
|
|
* before we go further. A counting loop is safe, as the HPET
|
|
* access takes thousands of CPU cycles. On non SB700 based
|
|
* machines this check is only done once and has no side
|
|
* effects.
|
|
*/
|
|
for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
|
|
if (i == 1000) {
|
|
printk(KERN_WARNING
|
|
"HPET config register value = 0xFFFFFFFF. "
|
|
"Disabling HPET\n");
|
|
goto out_nohpet;
|
|
}
|
|
}
|
|
|
|
if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
|
|
goto out_nohpet;
|
|
|
|
/*
|
|
* Read the HPET ID register to retrieve the IRQ routing
|
|
* information and the number of channels
|
|
*/
|
|
id = hpet_readl(HPET_ID);
|
|
|
|
#ifdef CONFIG_HPET_EMULATE_RTC
|
|
/*
|
|
* The legacy routing mode needs at least two channels, tick timer
|
|
* and the rtc emulation channel.
|
|
*/
|
|
if (!(id & HPET_ID_NUMBER))
|
|
goto out_nohpet;
|
|
#endif
|
|
|
|
if (hpet_clocksource_register())
|
|
goto out_nohpet;
|
|
|
|
if (id & HPET_ID_LEGSUP) {
|
|
hpet_legacy_clockevent_register();
|
|
hpet_msi_capability_lookup(2);
|
|
return 1;
|
|
}
|
|
hpet_msi_capability_lookup(0);
|
|
return 0;
|
|
|
|
out_nohpet:
|
|
hpet_clear_mapping();
|
|
boot_hpet_disable = 1;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Needs to be late, as the reserve_timer code calls kalloc !
|
|
*
|
|
* Not a problem on i386 as hpet_enable is called from late_time_init,
|
|
* but on x86_64 it is necessary !
|
|
*/
|
|
static __init int hpet_late_init(void)
|
|
{
|
|
int cpu;
|
|
|
|
if (boot_hpet_disable)
|
|
return -ENODEV;
|
|
|
|
if (!hpet_address) {
|
|
if (!force_hpet_address)
|
|
return -ENODEV;
|
|
|
|
hpet_address = force_hpet_address;
|
|
hpet_enable();
|
|
if (!hpet_virt_address)
|
|
return -ENODEV;
|
|
}
|
|
|
|
hpet_reserve_platform_timers(hpet_readl(HPET_ID));
|
|
|
|
for_each_online_cpu(cpu) {
|
|
hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
|
|
}
|
|
|
|
/* This notifier should be called after workqueue is ready */
|
|
hotcpu_notifier(hpet_cpuhp_notify, -20);
|
|
|
|
return 0;
|
|
}
|
|
fs_initcall(hpet_late_init);
|
|
|
|
void hpet_disable(void)
|
|
{
|
|
if (is_hpet_capable()) {
|
|
unsigned long cfg = hpet_readl(HPET_CFG);
|
|
|
|
if (hpet_legacy_int_enabled) {
|
|
cfg &= ~HPET_CFG_LEGACY;
|
|
hpet_legacy_int_enabled = 0;
|
|
}
|
|
cfg &= ~HPET_CFG_ENABLE;
|
|
hpet_writel(cfg, HPET_CFG);
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_HPET_EMULATE_RTC
|
|
|
|
/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
|
|
* is enabled, we support RTC interrupt functionality in software.
|
|
* RTC has 3 kinds of interrupts:
|
|
* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
|
|
* is updated
|
|
* 2) Alarm Interrupt - generate an interrupt at a specific time of day
|
|
* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
|
|
* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
|
|
* (1) and (2) above are implemented using polling at a frequency of
|
|
* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
|
|
* overhead. (DEFAULT_RTC_INT_FREQ)
|
|
* For (3), we use interrupts at 64Hz or user specified periodic
|
|
* frequency, whichever is higher.
|
|
*/
|
|
#include <linux/mc146818rtc.h>
|
|
#include <linux/rtc.h>
|
|
#include <asm/rtc.h>
|
|
|
|
#define DEFAULT_RTC_INT_FREQ 64
|
|
#define DEFAULT_RTC_SHIFT 6
|
|
#define RTC_NUM_INTS 1
|
|
|
|
static unsigned long hpet_rtc_flags;
|
|
static int hpet_prev_update_sec;
|
|
static struct rtc_time hpet_alarm_time;
|
|
static unsigned long hpet_pie_count;
|
|
static unsigned long hpet_t1_cmp;
|
|
static unsigned long hpet_default_delta;
|
|
static unsigned long hpet_pie_delta;
|
|
static unsigned long hpet_pie_limit;
|
|
|
|
static rtc_irq_handler irq_handler;
|
|
|
|
/*
|
|
* Registers a IRQ handler.
|
|
*/
|
|
int hpet_register_irq_handler(rtc_irq_handler handler)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return -ENODEV;
|
|
if (irq_handler)
|
|
return -EBUSY;
|
|
|
|
irq_handler = handler;
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
|
|
|
|
/*
|
|
* Deregisters the IRQ handler registered with hpet_register_irq_handler()
|
|
* and does cleanup.
|
|
*/
|
|
void hpet_unregister_irq_handler(rtc_irq_handler handler)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return;
|
|
|
|
irq_handler = NULL;
|
|
hpet_rtc_flags = 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
|
|
|
|
/*
|
|
* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
|
|
* is not supported by all HPET implementations for timer 1.
|
|
*
|
|
* hpet_rtc_timer_init() is called when the rtc is initialized.
|
|
*/
|
|
int hpet_rtc_timer_init(void)
|
|
{
|
|
unsigned long cfg, cnt, delta, flags;
|
|
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
if (!hpet_default_delta) {
|
|
uint64_t clc;
|
|
|
|
clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
|
|
clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
|
|
hpet_default_delta = (unsigned long) clc;
|
|
}
|
|
|
|
if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
|
|
delta = hpet_default_delta;
|
|
else
|
|
delta = hpet_pie_delta;
|
|
|
|
local_irq_save(flags);
|
|
|
|
cnt = delta + hpet_readl(HPET_COUNTER);
|
|
hpet_writel(cnt, HPET_T1_CMP);
|
|
hpet_t1_cmp = cnt;
|
|
|
|
cfg = hpet_readl(HPET_T1_CFG);
|
|
cfg &= ~HPET_TN_PERIODIC;
|
|
cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
|
|
hpet_writel(cfg, HPET_T1_CFG);
|
|
|
|
local_irq_restore(flags);
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
|
|
|
|
/*
|
|
* The functions below are called from rtc driver.
|
|
* Return 0 if HPET is not being used.
|
|
* Otherwise do the necessary changes and return 1.
|
|
*/
|
|
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
hpet_rtc_flags &= ~bit_mask;
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
|
|
|
|
int hpet_set_rtc_irq_bit(unsigned long bit_mask)
|
|
{
|
|
unsigned long oldbits = hpet_rtc_flags;
|
|
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
hpet_rtc_flags |= bit_mask;
|
|
|
|
if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
|
|
hpet_prev_update_sec = -1;
|
|
|
|
if (!oldbits)
|
|
hpet_rtc_timer_init();
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
|
|
|
|
int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
|
|
unsigned char sec)
|
|
{
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
hpet_alarm_time.tm_hour = hrs;
|
|
hpet_alarm_time.tm_min = min;
|
|
hpet_alarm_time.tm_sec = sec;
|
|
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
|
|
|
|
int hpet_set_periodic_freq(unsigned long freq)
|
|
{
|
|
uint64_t clc;
|
|
|
|
if (!is_hpet_enabled())
|
|
return 0;
|
|
|
|
if (freq <= DEFAULT_RTC_INT_FREQ)
|
|
hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
|
|
else {
|
|
clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
|
|
do_div(clc, freq);
|
|
clc >>= hpet_clockevent.shift;
|
|
hpet_pie_delta = (unsigned long) clc;
|
|
}
|
|
return 1;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
|
|
|
|
int hpet_rtc_dropped_irq(void)
|
|
{
|
|
return is_hpet_enabled();
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
|
|
|
|
static void hpet_rtc_timer_reinit(void)
|
|
{
|
|
unsigned long cfg, delta;
|
|
int lost_ints = -1;
|
|
|
|
if (unlikely(!hpet_rtc_flags)) {
|
|
cfg = hpet_readl(HPET_T1_CFG);
|
|
cfg &= ~HPET_TN_ENABLE;
|
|
hpet_writel(cfg, HPET_T1_CFG);
|
|
return;
|
|
}
|
|
|
|
if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
|
|
delta = hpet_default_delta;
|
|
else
|
|
delta = hpet_pie_delta;
|
|
|
|
/*
|
|
* Increment the comparator value until we are ahead of the
|
|
* current count.
|
|
*/
|
|
do {
|
|
hpet_t1_cmp += delta;
|
|
hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
|
|
lost_ints++;
|
|
} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
|
|
|
|
if (lost_ints) {
|
|
if (hpet_rtc_flags & RTC_PIE)
|
|
hpet_pie_count += lost_ints;
|
|
if (printk_ratelimit())
|
|
printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
|
|
lost_ints);
|
|
}
|
|
}
|
|
|
|
irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct rtc_time curr_time;
|
|
unsigned long rtc_int_flag = 0;
|
|
|
|
hpet_rtc_timer_reinit();
|
|
memset(&curr_time, 0, sizeof(struct rtc_time));
|
|
|
|
if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
|
|
get_rtc_time(&curr_time);
|
|
|
|
if (hpet_rtc_flags & RTC_UIE &&
|
|
curr_time.tm_sec != hpet_prev_update_sec) {
|
|
if (hpet_prev_update_sec >= 0)
|
|
rtc_int_flag = RTC_UF;
|
|
hpet_prev_update_sec = curr_time.tm_sec;
|
|
}
|
|
|
|
if (hpet_rtc_flags & RTC_PIE &&
|
|
++hpet_pie_count >= hpet_pie_limit) {
|
|
rtc_int_flag |= RTC_PF;
|
|
hpet_pie_count = 0;
|
|
}
|
|
|
|
if (hpet_rtc_flags & RTC_AIE &&
|
|
(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
|
|
(curr_time.tm_min == hpet_alarm_time.tm_min) &&
|
|
(curr_time.tm_hour == hpet_alarm_time.tm_hour))
|
|
rtc_int_flag |= RTC_AF;
|
|
|
|
if (rtc_int_flag) {
|
|
rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
|
|
if (irq_handler)
|
|
irq_handler(rtc_int_flag, dev_id);
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
|
|
#endif
|