forked from luck/tmp_suning_uos_patched
6a7f6ec951
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (25 commits) m68knommu: fix broken setting of irq_chip and handler m68knommu: switch to using -mcpu= flags for ColdFire targets m68knommu: arch/m68knommu/Kconfig whitespace cleanup m68knommu: create optimal separate instruction and data cache for ColdFire m68knommu: support ColdFire caches that do copyback and write-through m68knommu: support version 2 ColdFire split cache m68knommu: make cache push code ColdFire generic m68knommu: clean up ColdFire cache control code m68knommu: move inclusion of ColdFire v4 cache registers m68knommu: merge bit definitions for version 3 ColdFire cache controller m68knommu: create bit definitions for the version 2 ColdFire cache controller m68knommu: remove empty __iounmap() it is no used m68knommu: remove kernel_map() code, it is not used m68knommu: remove do_page_fault(), it is not used m68knommu: use user stack pointer hardware on some ColdFire cores m68knommu: remove command line printing DEBUG m68knommu: remove fasthandler interrupt code m68knommu: move UART addressing to part specific includes m68knommu: fix clock rate value reported for ColdFire 54xx parts m68knommu: move ColdFire CPU names into their headers ...
91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
/*
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* File: m54xxgpt.h
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* Purpose: Register and bit definitions for the MCF54XX
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*
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* Notes:
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*
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*/
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#ifndef m54xxgpt_h
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#define m54xxgpt_h
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/*********************************************************************
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*
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* General Purpose Timers (GPT)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_GPT_GMS0 0x000800
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#define MCF_GPT_GCIR0 0x000804
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#define MCF_GPT_GPWM0 0x000808
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#define MCF_GPT_GSR0 0x00080C
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#define MCF_GPT_GMS1 0x000810
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#define MCF_GPT_GCIR1 0x000814
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#define MCF_GPT_GPWM1 0x000818
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#define MCF_GPT_GSR1 0x00081C
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#define MCF_GPT_GMS2 0x000820
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#define MCF_GPT_GCIR2 0x000824
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#define MCF_GPT_GPWM2 0x000828
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#define MCF_GPT_GSR2 0x00082C
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#define MCF_GPT_GMS3 0x000830
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#define MCF_GPT_GCIR3 0x000834
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#define MCF_GPT_GPWM3 0x000838
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#define MCF_GPT_GSR3 0x00083C
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#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
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#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
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#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
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#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
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/* Bit definitions and macros for MCF_GPT_GMS */
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#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
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#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
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#define MCF_GPT_GMS_IEN (0x00000100)
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#define MCF_GPT_GMS_OD (0x00000200)
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#define MCF_GPT_GMS_SC (0x00000400)
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#define MCF_GPT_GMS_CE (0x00001000)
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#define MCF_GPT_GMS_WDEN (0x00008000)
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#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
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#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
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#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
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#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
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#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
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#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
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#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
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#define MCF_GPT_GMS_ICT_ANY (0x00000000)
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#define MCF_GPT_GMS_ICT_RISE (0x00010000)
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#define MCF_GPT_GMS_ICT_FALL (0x00020000)
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#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
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#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
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#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
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#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
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#define MCF_GPT_GMS_GPIO_MASK (0x00000030)
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#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
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#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
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#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
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#define MCF_GPT_GMS_TMS_PWM (0x00000003)
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#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
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#define MCF_GPT_GMS_TMS_MASK (0x00000007)
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/* Bit definitions and macros for MCF_GPT_GCIR */
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#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
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#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_GPT_GPWM */
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#define MCF_GPT_GPWM_LOAD (0x00000001)
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#define MCF_GPT_GPWM_PWMOP (0x00000100)
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#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for MCF_GPT_GSR */
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#define MCF_GPT_GSR_CAPT (0x00000001)
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#define MCF_GPT_GSR_COMP (0x00000002)
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#define MCF_GPT_GSR_PWMP (0x00000004)
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#define MCF_GPT_GSR_TEXP (0x00000008)
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#define MCF_GPT_GSR_PIN (0x00000100)
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#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
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#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
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/********************************************************************/
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#endif /* m54xxgpt_h */
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