forked from luck/tmp_suning_uos_patched
f007cacffc
This changes the writeX family of functions to have a sync instruction before the MMIO store rather than after, because the generally expected behaviour is that the device receiving the MMIO store can be guaranteed to see the effects of any preceding writes to normal memory. To preserve ordering between writeX and readX, and to preserve ordering between preceding stores and the readX, the readX family of functions have had an sync added before the load. Although writeX followed by spin_unlock is not officially guaranteed to keep the writeX inside the spin-locked region unless an mmiowb() is used, there are currently drivers that depend on the previous behaviour on powerpc, which was that the mmiowb wasn't actually required. Therefore we have a per-cpu flag that is set by writeX, cleared by __raw_spin_lock and mmiowb, and tested by __raw_spin_unlock. If it is set, __raw_spin_unlock does a sync and clears it. This changes both 32-bit and 64-bit readX/writeX. 32-bit already has a sync in __raw_spin_unlock (since lwsync doesn't exist on 32-bit), and thus doesn't need the per-cpu flag. Tested on G5 (PPC970) and POWER5. Signed-off-by: Paul Mackerras <paulus@samba.org>
587 lines
16 KiB
C
587 lines
16 KiB
C
#ifdef __KERNEL__
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#ifndef _PPC_IO_H
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#define _PPC_IO_H
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#include <linux/string.h>
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#include <linux/types.h>
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#include <asm/page.h>
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#include <asm/byteorder.h>
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#include <asm/synch.h>
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#include <asm/mmu.h>
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#define SIO_CONFIG_RA 0x398
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#define SIO_CONFIG_RD 0x399
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#define SLOW_DOWN_IO
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#define PMAC_ISA_MEM_BASE 0
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#define PMAC_PCI_DRAM_OFFSET 0
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#define CHRP_ISA_IO_BASE 0xf8000000
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#define CHRP_ISA_MEM_BASE 0xf7000000
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#define CHRP_PCI_DRAM_OFFSET 0
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#define PREP_ISA_IO_BASE 0x80000000
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#define PREP_ISA_MEM_BASE 0xc0000000
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#define PREP_PCI_DRAM_OFFSET 0x80000000
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#if defined(CONFIG_4xx)
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#include <asm/ibm4xx.h>
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#elif defined(CONFIG_PPC_MPC52xx)
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#include <asm/mpc52xx.h>
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#elif defined(CONFIG_8xx)
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#include <asm/mpc8xx.h>
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#elif defined(CONFIG_8260)
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#include <asm/mpc8260.h>
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#elif defined(CONFIG_83xx)
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#include <asm/mpc83xx.h>
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#elif defined(CONFIG_85xx)
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#include <asm/mpc85xx.h>
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#elif defined(CONFIG_APUS)
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#define _IO_BASE 0
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#define _ISA_MEM_BASE 0
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#define PCI_DRAM_OFFSET 0
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#else /* Everyone else */
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#define PCI_DRAM_OFFSET pci_dram_offset
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#endif /* Platform-dependent I/O */
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#define ___IO_BASE ((void __iomem *)_IO_BASE)
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extern unsigned long isa_io_base;
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extern unsigned long isa_mem_base;
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extern unsigned long pci_dram_offset;
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/*
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* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
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*
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* Read operations have additional twi & isync to make sure the read
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* is actually performed (i.e. the data has come back) before we start
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* executing any following instructions.
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*/
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extern inline int in_8(const volatile unsigned char __iomem *addr)
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{
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int ret;
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__asm__ __volatile__(
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"sync; lbz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_8(volatile unsigned char __iomem *addr, int val)
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{
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__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
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}
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extern inline int in_le16(const volatile unsigned short __iomem *addr)
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{
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int ret;
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__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline int in_be16(const volatile unsigned short __iomem *addr)
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{
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int ret;
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__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
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}
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extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
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{
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unsigned ret;
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__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) :
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"r" (addr), "m" (*addr));
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return ret;
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}
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extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
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{
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unsigned ret;
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__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
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"twi 0,%0,0;\n"
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"isync" : "=r" (ret) : "m" (*addr));
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return ret;
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}
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extern inline void out_le32(volatile unsigned __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
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"r" (val), "r" (addr));
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}
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extern inline void out_be32(volatile unsigned __iomem *addr, int val)
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{
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__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
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}
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#if defined (CONFIG_8260_PCI9)
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#define readb(addr) in_8((volatile u8 *)(addr))
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#define writeb(b,addr) out_8((volatile u8 *)(addr), (b))
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#else
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static inline __u8 readb(const volatile void __iomem *addr)
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{
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return in_8(addr);
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}
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static inline void writeb(__u8 b, volatile void __iomem *addr)
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{
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out_8(addr, b);
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}
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#endif
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#if defined(CONFIG_APUS)
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static inline __u16 readw(const volatile void __iomem *addr)
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{
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return *(__force volatile __u16 *)(addr);
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}
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static inline __u32 readl(const volatile void __iomem *addr)
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{
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return *(__force volatile __u32 *)(addr);
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}
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static inline void writew(__u16 b, volatile void __iomem *addr)
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{
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*(__force volatile __u16 *)(addr) = b;
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}
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static inline void writel(__u32 b, volatile void __iomem *addr)
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{
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*(__force volatile __u32 *)(addr) = b;
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}
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#elif defined (CONFIG_8260_PCI9)
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/* Use macros if PCI9 workaround enabled */
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#define readw(addr) in_le16((volatile u16 *)(addr))
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#define readl(addr) in_le32((volatile u32 *)(addr))
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#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
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#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
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#else
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static inline __u16 readw(const volatile void __iomem *addr)
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{
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return in_le16(addr);
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}
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static inline __u32 readl(const volatile void __iomem *addr)
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{
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return in_le32(addr);
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}
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static inline void writew(__u16 b, volatile void __iomem *addr)
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{
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out_le16(addr, b);
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}
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static inline void writel(__u32 b, volatile void __iomem *addr)
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{
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out_le32(addr, b);
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}
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#endif /* CONFIG_APUS */
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#define readb_relaxed(addr) readb(addr)
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#define readw_relaxed(addr) readw(addr)
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#define readl_relaxed(addr) readl(addr)
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static inline __u8 __raw_readb(const volatile void __iomem *addr)
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{
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return *(__force volatile __u8 *)(addr);
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}
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static inline __u16 __raw_readw(const volatile void __iomem *addr)
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{
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return *(__force volatile __u16 *)(addr);
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}
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static inline __u32 __raw_readl(const volatile void __iomem *addr)
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{
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return *(__force volatile __u32 *)(addr);
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}
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static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
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{
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*(__force volatile __u8 *)(addr) = b;
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}
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static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
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{
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*(__force volatile __u16 *)(addr) = b;
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}
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static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
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{
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*(__force volatile __u32 *)(addr) = b;
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}
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#define mmiowb()
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/*
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* The insw/outsw/insl/outsl macros don't do byte-swapping.
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* They are only used in practice for transferring buffers which
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* are arrays of bytes, and byte-swapping is not appropriate in
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* that case. - paulus
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*/
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#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
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#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
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#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
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#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
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#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
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#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
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/*
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* On powermacs and 8xx we will get a machine check exception
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* if we try to read data from a non-existent I/O port. Because
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* the machine check is an asynchronous exception, it isn't
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* well-defined which instruction SRR0 will point to when the
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* exception occurs.
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* With the sequence below (twi; isync; nop), we have found that
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* the machine check occurs on one of the three instructions on
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* all PPC implementations tested so far. The twi and isync are
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* needed on the 601 (in fact twi; sync works too), the isync and
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* nop are needed on 604[e|r], and any of twi, sync or isync will
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* work on 603[e], 750, 74xx.
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* The twi creates an explicit data dependency on the returned
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* value which seems to be needed to make the 601 wait for the
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* load to finish.
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*/
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#define __do_in_asm(name, op) \
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extern __inline__ unsigned int name(unsigned int port) \
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{ \
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unsigned int x; \
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__asm__ __volatile__( \
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"sync\n" \
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"0:" op " %0,0,%1\n" \
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"1: twi 0,%0,0\n" \
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"2: isync\n" \
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"3: nop\n" \
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"4:\n" \
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".section .fixup,\"ax\"\n" \
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"5: li %0,-1\n" \
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" b 4b\n" \
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".previous\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 0b,5b\n" \
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" .long 1b,5b\n" \
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" .long 2b,5b\n" \
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" .long 3b,5b\n" \
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".previous" \
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: "=&r" (x) \
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: "r" (port + ___IO_BASE)); \
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return x; \
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}
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#define __do_out_asm(name, op) \
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extern __inline__ void name(unsigned int val, unsigned int port) \
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{ \
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__asm__ __volatile__( \
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"sync\n" \
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"0:" op " %0,0,%1\n" \
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"1: sync\n" \
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"2:\n" \
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".section __ex_table,\"a\"\n" \
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" .align 2\n" \
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" .long 0b,2b\n" \
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" .long 1b,2b\n" \
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".previous" \
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: : "r" (val), "r" (port + ___IO_BASE)); \
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}
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__do_out_asm(outb, "stbx")
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#ifdef CONFIG_APUS
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__do_in_asm(inb, "lbzx")
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__do_in_asm(inw, "lhz%U1%X1")
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__do_in_asm(inl, "lwz%U1%X1")
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__do_out_asm(outl,"stw%U0%X0")
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__do_out_asm(outw, "sth%U0%X0")
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#elif defined (CONFIG_8260_PCI9)
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/* in asm cannot be defined if PCI9 workaround is used */
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#define inb(port) in_8((port)+___IO_BASE)
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#define inw(port) in_le16((port)+___IO_BASE)
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#define inl(port) in_le32((port)+___IO_BASE)
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__do_out_asm(outw, "sthbrx")
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__do_out_asm(outl, "stwbrx")
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#else
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__do_in_asm(inb, "lbzx")
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__do_in_asm(inw, "lhbrx")
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__do_in_asm(inl, "lwbrx")
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__do_out_asm(outw, "sthbrx")
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__do_out_asm(outl, "stwbrx")
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#endif
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#define inb_p(port) inb((port))
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#define outb_p(val, port) outb((val), (port))
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#define inw_p(port) inw((port))
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#define outw_p(val, port) outw((val), (port))
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#define inl_p(port) inl((port))
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#define outl_p(val, port) outl((val), (port))
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extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
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extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
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extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
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extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
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extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
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extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
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extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
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extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
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extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
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extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
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/*
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* The *_ns versions below don't do byte-swapping.
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* Neither do the standard versions now, these are just here
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* for older code.
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*/
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#define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
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#define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
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#define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
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#define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
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#define IO_SPACE_LIMIT ~0
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#if defined (CONFIG_8260_PCI9)
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#define memset_io(a,b,c) memset((void *)(a),(b),(c))
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#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
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#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
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#else
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static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
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{
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memset((void __force *)addr, val, count);
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}
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static inline void memcpy_fromio(void *dst,const volatile void __iomem *src, int count)
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{
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memcpy(dst, (void __force *) src, count);
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
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{
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memcpy((void __force *) dst, src, count);
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}
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#endif
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#define eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(void __force *)(void __iomem *)(b),(c),(d))
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/*
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* Map in an area of physical address space, for accessing
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* I/O devices etc.
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*/
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extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
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unsigned long flags);
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extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
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#ifdef CONFIG_44x
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extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
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#endif
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#define ioremap_nocache(addr, size) ioremap((addr), (size))
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extern void iounmap(volatile void __iomem *addr);
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extern unsigned long iopa(unsigned long addr);
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extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
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extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
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unsigned int size, int flags);
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/*
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* The PCI bus is inherently Little-Endian. The PowerPC is being
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* run Big-Endian. Thus all values which cross the [PCI] barrier
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* must be endian-adjusted. Also, the local DRAM has a different
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* address from the PCI point of view, thus buffer addresses also
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* have to be modified [mapped] appropriately.
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*/
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extern inline unsigned long virt_to_bus(volatile void * address)
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{
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#ifndef CONFIG_APUS
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if (address == (void *)0)
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return 0;
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return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
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#else
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return iopa ((unsigned long) address);
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#endif
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}
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extern inline void * bus_to_virt(unsigned long address)
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{
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#ifndef CONFIG_APUS
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if (address == 0)
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return NULL;
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return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
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#else
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return (void*) mm_ptov (address);
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#endif
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}
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/*
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* Change virtual addresses to physical addresses and vv, for
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* addresses in the area where the kernel has the RAM mapped.
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*/
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extern inline unsigned long virt_to_phys(volatile void * address)
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{
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#ifndef CONFIG_APUS
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return (unsigned long) address - KERNELBASE;
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#else
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return iopa ((unsigned long) address);
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#endif
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}
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extern inline void * phys_to_virt(unsigned long address)
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{
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#ifndef CONFIG_APUS
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return (void *) (address + KERNELBASE);
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#else
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return (void*) mm_ptov (address);
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#endif
|
|
}
|
|
|
|
/*
|
|
* Change "struct page" to physical address.
|
|
*/
|
|
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
|
|
#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
|
|
|
|
/* Enforce in-order execution of data I/O.
|
|
* No distinction between read/write on PPC; use eieio for all three.
|
|
*/
|
|
#define iobarrier_rw() eieio()
|
|
#define iobarrier_r() eieio()
|
|
#define iobarrier_w() eieio()
|
|
|
|
static inline int check_signature(volatile void __iomem * io_addr,
|
|
const unsigned char *signature, int length)
|
|
{
|
|
int retval = 0;
|
|
do {
|
|
if (readb(io_addr) != *signature)
|
|
goto out;
|
|
io_addr++;
|
|
signature++;
|
|
length--;
|
|
} while (length);
|
|
retval = 1;
|
|
out:
|
|
return retval;
|
|
}
|
|
|
|
/*
|
|
* Here comes the ppc implementation of the IOMAP
|
|
* interfaces.
|
|
*/
|
|
static inline unsigned int ioread8(void __iomem *addr)
|
|
{
|
|
return readb(addr);
|
|
}
|
|
|
|
static inline unsigned int ioread16(void __iomem *addr)
|
|
{
|
|
return readw(addr);
|
|
}
|
|
|
|
static inline unsigned int ioread32(void __iomem *addr)
|
|
{
|
|
return readl(addr);
|
|
}
|
|
|
|
static inline void iowrite8(u8 val, void __iomem *addr)
|
|
{
|
|
writeb(val, addr);
|
|
}
|
|
|
|
static inline void iowrite16(u16 val, void __iomem *addr)
|
|
{
|
|
writew(val, addr);
|
|
}
|
|
|
|
static inline void iowrite32(u32 val, void __iomem *addr)
|
|
{
|
|
writel(val, addr);
|
|
}
|
|
|
|
static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
|
|
{
|
|
_insb(addr, dst, count);
|
|
}
|
|
|
|
static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
|
|
{
|
|
_insw_ns(addr, dst, count);
|
|
}
|
|
|
|
static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
|
|
{
|
|
_insl_ns(addr, dst, count);
|
|
}
|
|
|
|
static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
|
|
{
|
|
_outsb(addr, src, count);
|
|
}
|
|
|
|
static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
|
|
{
|
|
_outsw_ns(addr, src, count);
|
|
}
|
|
|
|
static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
|
|
{
|
|
_outsl_ns(addr, src, count);
|
|
}
|
|
|
|
/* Create a virtual mapping cookie for an IO port range */
|
|
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
|
|
extern void ioport_unmap(void __iomem *);
|
|
|
|
/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
|
|
struct pci_dev;
|
|
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
|
|
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
|
|
|
|
#endif /* _PPC_IO_H */
|
|
|
|
#ifdef CONFIG_8260_PCI9
|
|
#include <asm/mpc8260_pci9.h>
|
|
#endif
|
|
|
|
#ifdef CONFIG_NOT_COHERENT_CACHE
|
|
|
|
#define dma_cache_inv(_start,_size) \
|
|
invalidate_dcache_range(_start, (_start + _size))
|
|
#define dma_cache_wback(_start,_size) \
|
|
clean_dcache_range(_start, (_start + _size))
|
|
#define dma_cache_wback_inv(_start,_size) \
|
|
flush_dcache_range(_start, (_start + _size))
|
|
|
|
#else
|
|
|
|
#define dma_cache_inv(_start,_size) do { } while (0)
|
|
#define dma_cache_wback(_start,_size) do { } while (0)
|
|
#define dma_cache_wback_inv(_start,_size) do { } while (0)
|
|
|
|
#endif
|
|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
|
|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
|
|
|
|
/* access ports */
|
|
#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
|
|
#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
|
|
|
|
#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
|
|
#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
|
|
|
|
#endif /* __KERNEL__ */
|