forked from luck/tmp_suning_uos_patched
9b791d4766
This patch fixes cache memory parameter setting for the M32104 target. So
far, its performance seemed to have been degraded due to incorrect cache
parameter setting.
* arch/m32r/boot/setup.S: Set SFR(Special Fuction Registers) region
to be non-cachable explicitly.
* arch/m32r/mm/cache.c: Fix cache flushing routines not to switch off
the M32104 cache.
Signed-off-by: Hayato Fujiwara <fujiwara@linux-m32r.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
186 lines
4.2 KiB
ArmAsm
186 lines
4.2 KiB
ArmAsm
/*
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* linux/arch/m32r/boot/setup.S -- A setup code.
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*
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* Copyright (C) 2001-2005 Hiroyuki Kondo, Hirokazu Takata,
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* Hitoshi Yamamoto, Hayato Fujiwara
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*
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*/
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <linux/config.h>
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#include <asm/assembler.h>
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#include <asm/mmu_context.h>
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#include <asm/m32r.h>
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/*
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* References to members of the boot_cpu_data structure.
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*/
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#define CPU_PARAMS boot_cpu_data
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#define M32R_MCICAR 0xfffffff0
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#define M32R_MCDCAR 0xfffffff4
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#define M32R_MCCR 0xfffffffc
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#define M32R_BSCR0 0xffffffd2
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;BSEL
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#define BSEL0CR0 0x00ef5000
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#define BSEL0CR1 0x00ef5004
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#define BSEL1CR0 0x00ef5100
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#define BSEL1CR1 0x00ef5104
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#define BSEL0CR0_VAL 0x00000000
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#define BSEL0CR1_VAL 0x01200100
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#define BSEL1CR0_VAL 0x01018000
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#define BSEL1CR1_VAL 0x00200001
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;SDRAMC
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#define SDRAMC_SDRF0 0x00ef6000
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#define SDRAMC_SDRF1 0x00ef6004
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#define SDRAMC_SDIR0 0x00ef6008
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#define SDRAMC_SDIR1 0x00ef600c
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#define SDRAMC_SD0ADR 0x00ef6020
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#define SDRAMC_SD0ER 0x00ef6024
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#define SDRAMC_SD0TR 0x00ef6028
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#define SDRAMC_SD0MOD 0x00ef602c
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#define SDRAMC_SD1ADR 0x00ef6040
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#define SDRAMC_SD1ER 0x00ef6044
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#define SDRAMC_SD1TR 0x00ef6048
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#define SDRAMC_SD1MOD 0x00ef604c
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#define SDRAM0 0x18000000
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#define SDRAM1 0x1c000000
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/*------------------------------------------------------------------------
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* start up
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*/
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/*------------------------------------------------------------------------
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* Kernel entry
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*/
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.section .boot, "ax"
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ENTRY(boot)
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/* Set cache mode */
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#if defined(CONFIG_CHIP_XNUX2)
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ldi r0, #-2 ;LDIMM (r0, M32R_MCCR)
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ldi r1, #0x0101 ; cache on (with invalidation)
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; ldi r1, #0x00 ; cache off
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sth r1, @r0
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#elif defined(CONFIG_CHIP_M32700) || defined(CONFIG_CHIP_VDEC2) \
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|| defined(CONFIG_CHIP_OPSP)
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ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
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ldi r1, #0x73 ; cache on (with invalidation)
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; ldi r1, #0x00 ; cache off
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st r1, @r0
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#elif defined(CONFIG_CHIP_M32102)
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ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
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ldi r1, #0x101 ; cache on (with invalidation)
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; ldi r1, #0x00 ; cache off
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st r1, @r0
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#elif defined(CONFIG_CHIP_M32104)
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ldi r0, #-96 ; DNCR0
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seth r1, #0x0060 ; from 0x00600000
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or3 r1, r1, #0x0005 ; size 2MB
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st r1, @r0
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seth r1, #0x0100 ; from 0x01000000
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or3 r1, r1, #0x0003 ; size 16MB
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st r1, @+r0
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seth r1, #0x0200 ; from 0x02000000
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or3 r1, r1, #0x0002 ; size 32MB
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st r1, @+r0
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ldi r0, #-4 ;LDIMM (r0, M32R_MCCR)
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ldi r1, #0x703 ; cache on (with invalidation)
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st r1, @r0
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#else
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#error unknown chip configuration
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#endif
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#ifdef CONFIG_SMP
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;; if not BSP (CPU#0) goto AP_loop
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seth r5, #shigh(M32R_CPUID_PORTL)
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ld r5, @(low(M32R_CPUID_PORTL), r5)
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bnez r5, AP_loop
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#if !defined(CONFIG_PLAT_USRV)
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;; boot AP
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ld24 r5, #0xeff2f8 ; IPICR7
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ldi r6, #0x2 ; IPI to CPU1
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st r6, @r5
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#endif
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#endif
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/*
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* Now, Jump to stext
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* if with MMU, TLB on.
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* if with no MMU, only jump.
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*/
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.global eit_vector
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mmu_on:
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LDIMM (r13, stext)
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#ifdef CONFIG_MMU
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bl init_tlb
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LDIMM (r2, eit_vector) ; set EVB(cr5)
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mvtc r2, cr5
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seth r0, #high(MMU_REG_BASE) ; Set MMU_REG_BASE higher
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or3 r0, r0, #low(MMU_REG_BASE) ; Set MMU_REG_BASE lower
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ldi r1, #0x01
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st r1, @(MATM_offset,r0) ; Set MATM (T bit ON)
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ld r0, @(MATM_offset,r0) ; Check
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#else
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#if defined(CONFIG_CHIP_M32700)
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seth r0,#high(M32R_MCDCAR)
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or3 r0,r0,#low(M32R_MCDCAR)
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ld24 r1,#0x8080
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st r1,@r0
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#elif defined(CONFIG_CHIP_M32104)
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LDIMM (r2, eit_vector) ; set EVB(cr5)
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mvtc r2, cr5
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#endif
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#endif /* CONFIG_MMU */
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jmp r13
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nop
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nop
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#ifdef CONFIG_SMP
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/*
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* AP wait loop
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*/
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ENTRY(AP_loop)
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;; disable interrupt
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clrpsw #0x40
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;; reset EVB
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LDIMM (r4, _AP_RE)
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seth r5, #high(__PAGE_OFFSET)
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or3 r5, r5, #low(__PAGE_OFFSET)
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not r5, r5
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and r4, r5
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mvtc r4, cr5
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;; disable maskable interrupt
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seth r4, #high(M32R_ICU_IMASK_PORTL)
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or3 r4, r4, #low(M32R_ICU_IMASK_PORTL)
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ldi r5, #0
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st r5, @r4
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ld r5, @r4
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;; enable only IPI
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setpsw #0x40
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;; LOOOOOOOOOOOOOOP!!!
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.fillinsn
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2:
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nop
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nop
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bra 2b
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nop
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nop
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#ifdef CONFIG_CHIP_M32700_TS1
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.global dcache_dummy
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.balign 16, 0
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dcache_dummy:
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.byte 16
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#endif /* CONFIG_CHIP_M32700_TS1 */
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#endif /* CONFIG_SMP */
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.end
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