forked from luck/tmp_suning_uos_patched
fa6a940bf1
max_bytes_per_lli = bd.srcbus.buswidth * PL080_CONTROL_TRANSFER_SIZE_MASK; This is confirmed by ARM support guys. Below is summary of mail exchange with them: [Viresh] What is the total data to be transferred in case source and destination bus widths are different. Suppose, source bus width is 2 bytes and destination is 4 bytes. Now in order to transfer 80 bytes, what should be value of TransferSize field in control reg: 40? or 20?. [David from ARM] The value that is programmed into the TransferSize field should be the number of <SourceWidth> transfers needed to achieve the required data transfer. So, to transfer 80 bytes, with a Source Width of 2, the TransferSize field = should be programmed with: Total transfer size ------------------- = 40 <source width> [Viresh] Will this change if source is 4 bytes and dest is 2? [David] Yes - the calculation then becomes: Total transfer size ------------------- =20 <source width> Also, max_bytes_per_lli must be calculated after fixing src and dest widths not before that. So move this code to the correct place. This patch also removes max_bytes_per_lli from earlier print message, as till that point max_bytes_per_lli is unknown. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com> |
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.. | ||
ioat | ||
ipu | ||
ppc4xx | ||
amba-pl08x.c | ||
at_hdmac_regs.h | ||
at_hdmac.c | ||
coh901318_lli.c | ||
coh901318_lli.h | ||
coh901318.c | ||
dmaengine.c | ||
dmatest.c | ||
dw_dmac_regs.h | ||
dw_dmac.c | ||
ep93xx_dma.c | ||
fsldma.c | ||
fsldma.h | ||
imx-dma.c | ||
imx-sdma.c | ||
intel_mid_dma_regs.h | ||
intel_mid_dma.c | ||
iop-adma.c | ||
iovlock.c | ||
Kconfig | ||
Makefile | ||
mpc512x_dma.c | ||
mv_xor.c | ||
mv_xor.h | ||
mxs-dma.c | ||
pch_dma.c | ||
pl330.c | ||
shdma.c | ||
shdma.h | ||
ste_dma40_ll.c | ||
ste_dma40_ll.h | ||
ste_dma40.c | ||
timb_dma.c | ||
TODO | ||
txx9dmac.c | ||
txx9dmac.h |