forked from luck/tmp_suning_uos_patched
6e668936db
- Enable kernel generic spidev driver for blackfin SPI ADC - spi_adc driver, document and test sample not synced Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
/************************************************************
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* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
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*
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* FILE bfin5xx_spi.h
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* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
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*
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*
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* DATE OF CREATION: March. 10th 2006
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*
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* SYNOPSIS:
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*
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* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
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**************************************************************
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* MODIFICATION HISTORY:
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* March 10, 2006 bfin5xx_spi.h Created. (Luke Yang)
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************************************************************/
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#ifndef _SPI_CHANNEL_H_
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#define _SPI_CHANNEL_H_
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#define SPI_READ 0
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#define SPI_WRITE 1
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#define SPI_CTRL_OFF 0x0
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#define SPI_FLAG_OFF 0x4
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#define SPI_STAT_OFF 0x8
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#define SPI_TXBUFF_OFF 0xc
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#define SPI_RXBUFF_OFF 0x10
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#define SPI_BAUD_OFF 0x14
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#define SPI_SHAW_OFF 0x18
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#define BIT_CTL_ENABLE 0x4000
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#define BIT_CTL_OPENDRAIN 0x2000
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#define BIT_CTL_MASTER 0x1000
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#define BIT_CTL_POLAR 0x0800
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#define BIT_CTL_PHASE 0x0400
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#define BIT_CTL_BITORDER 0x0200
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#define BIT_CTL_WORDSIZE 0x0100
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#define BIT_CTL_MISOENABLE 0x0020
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#define BIT_CTL_RXMOD 0x0000
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#define BIT_CTL_TXMOD 0x0001
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#define BIT_CTL_TIMOD_DMA_TX 0x0003
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#define BIT_CTL_TIMOD_DMA_RX 0x0002
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#define BIT_CTL_SENDOPT 0x0004
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#define BIT_CTL_TIMOD 0x0003
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#define BIT_STAT_SPIF 0x0001
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#define BIT_STAT_MODF 0x0002
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#define BIT_STAT_TXE 0x0004
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#define BIT_STAT_TXS 0x0008
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#define BIT_STAT_RBSY 0x0010
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#define BIT_STAT_RXS 0x0020
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#define BIT_STAT_TXCOL 0x0040
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#define BIT_STAT_CLR 0xFFFF
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#define BIT_STU_SENDOVER 0x0001
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#define BIT_STU_RECVFULL 0x0020
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#define CFG_SPI_ENABLE 1
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#define CFG_SPI_DISABLE 0
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#define CFG_SPI_OUTENABLE 1
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#define CFG_SPI_OUTDISABLE 0
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#define CFG_SPI_ACTLOW 1
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#define CFG_SPI_ACTHIGH 0
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#define CFG_SPI_PHASESTART 1
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#define CFG_SPI_PHASEMID 0
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#define CFG_SPI_MASTER 1
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#define CFG_SPI_SLAVE 0
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#define CFG_SPI_SENELAST 0
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#define CFG_SPI_SENDZERO 1
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#define CFG_SPI_RCVFLUSH 1
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#define CFG_SPI_RCVDISCARD 0
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#define CFG_SPI_LSBFIRST 1
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#define CFG_SPI_MSBFIRST 0
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#define CFG_SPI_WORDSIZE16 1
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#define CFG_SPI_WORDSIZE8 0
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#define CFG_SPI_MISOENABLE 1
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#define CFG_SPI_MISODISABLE 0
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#define CFG_SPI_READ 0x00
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#define CFG_SPI_WRITE 0x01
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#define CFG_SPI_DMAREAD 0x02
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#define CFG_SPI_DMAWRITE 0x03
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#define CFG_SPI_CSCLEARALL 0
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#define CFG_SPI_CHIPSEL1 1
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#define CFG_SPI_CHIPSEL2 2
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#define CFG_SPI_CHIPSEL3 3
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#define CFG_SPI_CHIPSEL4 4
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#define CFG_SPI_CHIPSEL5 5
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#define CFG_SPI_CHIPSEL6 6
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#define CFG_SPI_CHIPSEL7 7
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#define CFG_SPI_CS1VALUE 1
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#define CFG_SPI_CS2VALUE 2
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#define CFG_SPI_CS3VALUE 3
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#define CFG_SPI_CS4VALUE 4
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#define CFG_SPI_CS5VALUE 5
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#define CFG_SPI_CS6VALUE 6
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#define CFG_SPI_CS7VALUE 7
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#define CMD_SPI_SET_BAUDRATE 2
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#define CMD_SPI_GET_SYSTEMCLOCK 25
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#define CMD_SPI_SET_WRITECONTINUOUS 26
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/* device.platform_data for SSP controller devices */
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struct bfin5xx_spi_master {
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u16 num_chipselect;
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u8 enable_dma;
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u16 pin_req[4];
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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*/
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struct bfin5xx_spi_chip {
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u16 ctl_reg;
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u8 enable_dma;
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u8 bits_per_word;
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u8 cs_change_per_word;
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u16 cs_chg_udelay; /* Some devices require 16-bit delays */
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};
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#endif /* _SPI_CHANNEL_H_ */
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