forked from luck/tmp_suning_uos_patched
f64e8084c9
No code changes. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
516 lines
12 KiB
ArmAsm
516 lines
12 KiB
ArmAsm
/*
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* This file contains the power_save function for Power7 CPUs.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/threads.h>
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#include <asm/processor.h>
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#include <asm/page.h>
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#include <asm/cputable.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ppc-opcode.h>
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#include <asm/hw_irq.h>
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#include <asm/kvm_book3s_asm.h>
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#include <asm/opal.h>
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#include <asm/cpuidle.h>
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#include <asm/book3s/64/mmu-hash.h>
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#undef DEBUG
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/*
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* Use unused space in the interrupt stack to save and restore
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* registers for winkle support.
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*/
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#define _SDR1 GPR3
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#define _RPR GPR4
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#define _SPURR GPR5
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#define _PURR GPR6
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#define _TSCR GPR7
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#define _DSCR GPR8
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#define _AMOR GPR9
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#define _WORT GPR10
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#define _WORC GPR11
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/* Idle state entry routines */
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#define IDLE_STATE_ENTER_SEQ(IDLE_INST) \
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/* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
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std r0,0(r1); \
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ptesync; \
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ld r0,0(r1); \
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1: cmp cr0,r0,r0; \
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bne 1b; \
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IDLE_INST; \
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b .
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.text
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/*
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* Used by threads when the lock bit of core_idle_state is set.
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* Threads will spin in HMT_LOW until the lock bit is cleared.
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* r14 - pointer to core_idle_state
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* r15 - used to load contents of core_idle_state
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*/
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core_idle_lock_held:
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HMT_LOW
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3: lwz r15,0(r14)
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andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
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bne 3b
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HMT_MEDIUM
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lwarx r15,0,r14
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blr
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/*
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* Pass requested state in r3:
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* r3 - PNV_THREAD_NAP/SLEEP/WINKLE
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*
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* To check IRQ_HAPPENED in r4
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* 0 - don't check
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* 1 - check
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*/
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_GLOBAL(power7_powersave_common)
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/* Use r3 to pass state nap/sleep/winkle */
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/* NAP is a state loss, we create a regs frame on the
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* stack, fill it up with the state we care about and
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* stick a pointer to it in PACAR1. We really only
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* need to save PC, some CR bits and the NV GPRs,
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* but for now an interrupt frame will do.
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*/
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mflr r0
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std r0,16(r1)
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stdu r1,-INT_FRAME_SIZE(r1)
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std r0,_LINK(r1)
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std r0,_NIP(r1)
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/* Hard disable interrupts */
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mfmsr r9
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rldicl r9,r9,48,1
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rotldi r9,r9,16
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mtmsrd r9,1 /* hard-disable interrupts */
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/* Check if something happened while soft-disabled */
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lbz r0,PACAIRQHAPPENED(r13)
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andi. r0,r0,~PACA_IRQ_HARD_DIS@l
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beq 1f
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cmpwi cr0,r4,0
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beq 1f
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addi r1,r1,INT_FRAME_SIZE
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ld r0,16(r1)
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li r3,0 /* Return 0 (no nap) */
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mtlr r0
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blr
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1: /* We mark irqs hard disabled as this is the state we'll
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* be in when returning and we need to tell arch_local_irq_restore()
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* about it
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*/
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li r0,PACA_IRQ_HARD_DIS
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stb r0,PACAIRQHAPPENED(r13)
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/* We haven't lost state ... yet */
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li r0,0
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stb r0,PACA_NAPSTATELOST(r13)
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/* Continue saving state */
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SAVE_GPR(2, r1)
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SAVE_NVGPRS(r1)
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mfcr r4
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std r4,_CCR(r1)
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std r9,_MSR(r1)
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std r1,PACAR1(r13)
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/*
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* Go to real mode to do the nap, as required by the architecture.
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* Also, we need to be in real mode before setting hwthread_state,
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* because as soon as we do that, another thread can switch
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* the MMU context to the guest.
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*/
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LOAD_REG_IMMEDIATE(r5, MSR_IDLE)
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li r6, MSR_RI
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andc r6, r9, r6
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LOAD_REG_ADDR(r7, power7_enter_nap_mode)
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mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
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mtspr SPRN_SRR0, r7
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mtspr SPRN_SRR1, r5
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rfid
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.globl power7_enter_nap_mode
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power7_enter_nap_mode:
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/* Tell KVM we're napping */
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li r4,KVM_HWTHREAD_IN_NAP
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stb r4,HSTATE_HWTHREAD_STATE(r13)
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#endif
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stb r3,PACA_THREAD_IDLE_STATE(r13)
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cmpwi cr3,r3,PNV_THREAD_SLEEP
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bge cr3,2f
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IDLE_STATE_ENTER_SEQ(PPC_NAP)
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/* No return */
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2:
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/* Sleep or winkle */
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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lwarx_loop1:
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lwarx r15,0,r14
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andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
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bnel core_idle_lock_held
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andc r15,r15,r7 /* Clear thread bit */
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andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
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/*
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* If cr0 = 0, then current thread is the last thread of the core entering
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* sleep. Last thread needs to execute the hardware bug workaround code if
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* required by the platform.
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* Make the workaround call unconditionally here. The below branch call is
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* patched out when the idle states are discovered if the platform does not
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* require it.
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*/
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.global pnv_fastsleep_workaround_at_entry
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pnv_fastsleep_workaround_at_entry:
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beq fastsleep_workaround_at_entry
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stwcx. r15,0,r14
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bne- lwarx_loop1
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isync
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common_enter: /* common code for all the threads entering sleep or winkle */
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bgt cr3,enter_winkle
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IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
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fastsleep_workaround_at_entry:
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ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
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stwcx. r15,0,r14
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bne- lwarx_loop1
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isync
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/* Fast sleep workaround */
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li r3,1
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li r4,1
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li r0,OPAL_CONFIG_CPU_IDLE_STATE
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bl opal_call_realmode
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/* Clear Lock bit */
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li r0,0
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lwsync
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stw r0,0(r14)
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b common_enter
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enter_winkle:
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/*
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* Note all register i.e per-core, per-subcore or per-thread is saved
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* here since any thread in the core might wake up first
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*/
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mfspr r3,SPRN_SDR1
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std r3,_SDR1(r1)
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mfspr r3,SPRN_RPR
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std r3,_RPR(r1)
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mfspr r3,SPRN_SPURR
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std r3,_SPURR(r1)
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mfspr r3,SPRN_PURR
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std r3,_PURR(r1)
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mfspr r3,SPRN_TSCR
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std r3,_TSCR(r1)
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mfspr r3,SPRN_DSCR
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std r3,_DSCR(r1)
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mfspr r3,SPRN_AMOR
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std r3,_AMOR(r1)
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mfspr r3,SPRN_WORT
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std r3,_WORT(r1)
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mfspr r3,SPRN_WORC
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std r3,_WORC(r1)
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IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
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_GLOBAL(power7_idle)
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/* Now check if user or arch enabled NAP mode */
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LOAD_REG_ADDRBASE(r3,powersave_nap)
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lwz r4,ADDROFF(powersave_nap)(r3)
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cmpwi 0,r4,0
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beqlr
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li r3, 1
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/* fall through */
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_GLOBAL(power7_nap)
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mr r4,r3
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li r3,PNV_THREAD_NAP
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b power7_powersave_common
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/* No return */
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_GLOBAL(power7_sleep)
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li r3,PNV_THREAD_SLEEP
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li r4,1
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b power7_powersave_common
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/* No return */
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_GLOBAL(power7_winkle)
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li r3,3
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li r4,1
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b power7_powersave_common
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/* No return */
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#define CHECK_HMI_INTERRUPT \
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mfspr r0,SPRN_SRR1; \
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BEGIN_FTR_SECTION_NESTED(66); \
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rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
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FTR_SECTION_ELSE_NESTED(66); \
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rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
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ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
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cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
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bne 20f; \
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/* Invoke opal call to handle hmi */ \
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ld r2,PACATOC(r13); \
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ld r1,PACAR1(r13); \
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std r3,ORIG_GPR3(r1); /* Save original r3 */ \
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li r0,OPAL_HANDLE_HMI; /* Pass opal token argument*/ \
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bl opal_call_realmode; \
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ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
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20: nop;
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_GLOBAL(power7_wakeup_tb_loss)
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ld r2,PACATOC(r13);
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ld r1,PACAR1(r13)
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/*
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* Before entering any idle state, the NVGPRs are saved in the stack
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* and they are restored before switching to the process context. Hence
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* until they are restored, they are free to be used.
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*
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* Save SRR1 in a NVGPR as it might be clobbered in opal_call_realmode
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* (called in CHECK_HMI_INTERRUPT). SRR1 is required to determine the
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* wakeup reason if we branch to kvm_start_guest.
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*/
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mfspr r16,SPRN_SRR1
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BEGIN_FTR_SECTION
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CHECK_HMI_INTERRUPT
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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lbz r7,PACA_THREAD_MASK(r13)
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ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
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lwarx_loop2:
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lwarx r15,0,r14
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andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
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/*
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* Lock bit is set in one of the 2 cases-
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* a. In the sleep/winkle enter path, the last thread is executing
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* fastsleep workaround code.
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* b. In the wake up path, another thread is executing fastsleep
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* workaround undo code or resyncing timebase or restoring context
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* In either case loop until the lock bit is cleared.
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*/
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bnel core_idle_lock_held
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cmpwi cr2,r15,0
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lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
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and r4,r4,r15
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cmpwi cr1,r4,0 /* Check if first in subcore */
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/*
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* At this stage
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* cr1 - 0b0100 if first thread to wakeup in subcore
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* cr2 - 0b0100 if first thread to wakeup in core
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* cr3- 0b0010 if waking up from sleep or winkle
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* cr4 - 0b0100 if waking up from winkle
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*/
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or r15,r15,r7 /* Set thread bit */
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beq cr1,first_thread_in_subcore
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/* Not first thread in subcore to wake up */
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stwcx. r15,0,r14
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bne- lwarx_loop2
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isync
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b common_exit
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first_thread_in_subcore:
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/* First thread in subcore to wakeup */
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ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
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stwcx. r15,0,r14
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bne- lwarx_loop2
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isync
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/*
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* If waking up from sleep, subcore state is not lost. Hence
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* skip subcore state restore
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*/
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bne cr4,subcore_state_restored
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/* Restore per-subcore state */
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ld r4,_SDR1(r1)
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mtspr SPRN_SDR1,r4
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ld r4,_RPR(r1)
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mtspr SPRN_RPR,r4
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ld r4,_AMOR(r1)
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mtspr SPRN_AMOR,r4
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subcore_state_restored:
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/*
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* Check if the thread is also the first thread in the core. If not,
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* skip to clear_lock.
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*/
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bne cr2,clear_lock
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first_thread_in_core:
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/*
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* First thread in the core waking up from fastsleep. It needs to
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* call the fastsleep workaround code if the platform requires it.
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* Call it unconditionally here. The below branch instruction will
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* be patched out when the idle states are discovered if platform
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* does not require workaround.
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*/
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.global pnv_fastsleep_workaround_at_exit
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pnv_fastsleep_workaround_at_exit:
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b fastsleep_workaround_at_exit
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timebase_resync:
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/* Do timebase resync if we are waking up from sleep. Use cr3 value
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* set in exceptions-64s.S */
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ble cr3,clear_lock
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/* Time base re-sync */
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li r0,OPAL_RESYNC_TIMEBASE
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bl opal_call_realmode;
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/* TODO: Check r3 for failure */
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/*
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* If waking up from sleep, per core state is not lost, skip to
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* clear_lock.
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*/
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bne cr4,clear_lock
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/* Restore per core state */
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ld r4,_TSCR(r1)
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mtspr SPRN_TSCR,r4
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ld r4,_WORC(r1)
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mtspr SPRN_WORC,r4
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clear_lock:
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andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
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lwsync
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stw r15,0(r14)
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common_exit:
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/*
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* Common to all threads.
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*
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* If waking up from sleep, hypervisor state is not lost. Hence
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* skip hypervisor state restore.
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*/
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bne cr4,hypervisor_state_restored
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/* Waking up from winkle */
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/* Restore per thread state */
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bl __restore_cpu_power8
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/* Restore SLB from PACA */
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ld r8,PACA_SLBSHADOWPTR(r13)
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.rept SLB_NUM_BOLTED
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li r3, SLBSHADOW_SAVEAREA
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LDX_BE r5, r8, r3
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addi r3, r3, 8
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LDX_BE r6, r8, r3
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andis. r7,r5,SLB_ESID_V@h
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beq 1f
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slbmte r6,r5
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1: addi r8,r8,16
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.endr
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ld r4,_SPURR(r1)
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mtspr SPRN_SPURR,r4
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ld r4,_PURR(r1)
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mtspr SPRN_PURR,r4
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ld r4,_DSCR(r1)
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mtspr SPRN_DSCR,r4
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ld r4,_WORT(r1)
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mtspr SPRN_WORT,r4
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hypervisor_state_restored:
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li r5,PNV_THREAD_RUNNING
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stb r5,PACA_THREAD_IDLE_STATE(r13)
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mtspr SPRN_SRR1,r16
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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li r0,KVM_HWTHREAD_IN_KERNEL
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stb r0,HSTATE_HWTHREAD_STATE(r13)
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/* Order setting hwthread_state vs. testing hwthread_req */
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sync
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lbz r0,HSTATE_HWTHREAD_REQ(r13)
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cmpwi r0,0
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beq 6f
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b kvm_start_guest
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6:
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#endif
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REST_NVGPRS(r1)
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REST_GPR(2, r1)
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ld r3,_CCR(r1)
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ld r4,_MSR(r1)
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ld r5,_NIP(r1)
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addi r1,r1,INT_FRAME_SIZE
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mtcr r3
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mfspr r3,SPRN_SRR1 /* Return SRR1 */
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mtspr SPRN_SRR1,r4
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mtspr SPRN_SRR0,r5
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rfid
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fastsleep_workaround_at_exit:
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li r3,1
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li r4,0
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li r0,OPAL_CONFIG_CPU_IDLE_STATE
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bl opal_call_realmode
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b timebase_resync
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/*
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* R3 here contains the value that will be returned to the caller
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* of power7_nap.
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*/
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_GLOBAL(power7_wakeup_loss)
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ld r1,PACAR1(r13)
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BEGIN_FTR_SECTION
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CHECK_HMI_INTERRUPT
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END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
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REST_NVGPRS(r1)
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REST_GPR(2, r1)
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ld r6,_CCR(r1)
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ld r4,_MSR(r1)
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ld r5,_NIP(r1)
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addi r1,r1,INT_FRAME_SIZE
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mtcr r6
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mtspr SPRN_SRR1,r4
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mtspr SPRN_SRR0,r5
|
|
rfid
|
|
|
|
/*
|
|
* R3 here contains the value that will be returned to the caller
|
|
* of power7_nap.
|
|
*/
|
|
_GLOBAL(power7_wakeup_noloss)
|
|
lbz r0,PACA_NAPSTATELOST(r13)
|
|
cmpwi r0,0
|
|
bne power7_wakeup_loss
|
|
BEGIN_FTR_SECTION
|
|
CHECK_HMI_INTERRUPT
|
|
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
|
|
ld r1,PACAR1(r13)
|
|
ld r6,_CCR(r1)
|
|
ld r4,_MSR(r1)
|
|
ld r5,_NIP(r1)
|
|
addi r1,r1,INT_FRAME_SIZE
|
|
mtcr r6
|
|
mtspr SPRN_SRR1,r4
|
|
mtspr SPRN_SRR0,r5
|
|
rfid
|