forked from luck/tmp_suning_uos_patched
21b4991051
I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad can be used to control the common voltage signal level and power state of the pins in the given pad. I/O pads can be powered down even if the system is active, which can save power from that I/O interface. For SoC generations prior to Tegra124 the I/O pad voltage is automatically detected and hence the system software doesn't need to configure it. However, starting with Tegra210 the detection logic has been removed, so explicit control of the I/O pad voltage by system software is required. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
227 lines
5.6 KiB
C
227 lines
5.6 KiB
C
/*
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* Copyright (c) 2010 Google, Inc
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* Copyright (c) 2014 NVIDIA Corporation
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*
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* Author:
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* Colin Cross <ccross@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __SOC_TEGRA_PMC_H__
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#define __SOC_TEGRA_PMC_H__
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#include <linux/reboot.h>
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#include <soc/tegra/pm.h>
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struct clk;
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struct reset_control;
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#ifdef CONFIG_PM_SLEEP
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enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
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void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
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void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
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#endif /* CONFIG_PM_SLEEP */
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#ifdef CONFIG_SMP
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bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
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int tegra_pmc_cpu_power_on(unsigned int cpuid);
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int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
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#endif /* CONFIG_SMP */
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/*
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* powergate and I/O rail APIs
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*/
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#define TEGRA_POWERGATE_CPU 0
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#define TEGRA_POWERGATE_3D 1
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#define TEGRA_POWERGATE_VENC 2
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#define TEGRA_POWERGATE_PCIE 3
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#define TEGRA_POWERGATE_VDEC 4
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#define TEGRA_POWERGATE_L2 5
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#define TEGRA_POWERGATE_MPE 6
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#define TEGRA_POWERGATE_HEG 7
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#define TEGRA_POWERGATE_SATA 8
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#define TEGRA_POWERGATE_CPU1 9
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#define TEGRA_POWERGATE_CPU2 10
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#define TEGRA_POWERGATE_CPU3 11
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#define TEGRA_POWERGATE_CELP 12
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#define TEGRA_POWERGATE_3D1 13
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#define TEGRA_POWERGATE_CPU0 14
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#define TEGRA_POWERGATE_C0NC 15
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#define TEGRA_POWERGATE_C1NC 16
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#define TEGRA_POWERGATE_SOR 17
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#define TEGRA_POWERGATE_DIS 18
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#define TEGRA_POWERGATE_DISB 19
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#define TEGRA_POWERGATE_XUSBA 20
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#define TEGRA_POWERGATE_XUSBB 21
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#define TEGRA_POWERGATE_XUSBC 22
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#define TEGRA_POWERGATE_VIC 23
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#define TEGRA_POWERGATE_IRAM 24
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#define TEGRA_POWERGATE_NVDEC 25
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#define TEGRA_POWERGATE_NVJPG 26
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#define TEGRA_POWERGATE_AUD 27
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#define TEGRA_POWERGATE_DFD 28
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#define TEGRA_POWERGATE_VE2 29
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#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
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#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
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/**
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* enum tegra_io_pad - I/O pad group identifier
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*
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* I/O pins on Tegra SoCs are grouped into so-called I/O pads. Each such pad
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* can be used to control the common voltage signal level and power state of
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* the pins of the given pad.
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*/
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enum tegra_io_pad {
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TEGRA_IO_PAD_AUDIO,
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TEGRA_IO_PAD_AUDIO_HV,
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TEGRA_IO_PAD_BB,
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TEGRA_IO_PAD_CAM,
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TEGRA_IO_PAD_COMP,
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TEGRA_IO_PAD_CSIA,
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TEGRA_IO_PAD_CSIB,
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TEGRA_IO_PAD_CSIC,
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TEGRA_IO_PAD_CSID,
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TEGRA_IO_PAD_CSIE,
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TEGRA_IO_PAD_CSIF,
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TEGRA_IO_PAD_DBG,
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TEGRA_IO_PAD_DEBUG_NONAO,
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TEGRA_IO_PAD_DMIC,
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TEGRA_IO_PAD_DP,
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TEGRA_IO_PAD_DSI,
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TEGRA_IO_PAD_DSIB,
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TEGRA_IO_PAD_DSIC,
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TEGRA_IO_PAD_DSID,
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TEGRA_IO_PAD_EMMC,
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TEGRA_IO_PAD_EMMC2,
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TEGRA_IO_PAD_GPIO,
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TEGRA_IO_PAD_HDMI,
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TEGRA_IO_PAD_HSIC,
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TEGRA_IO_PAD_HV,
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TEGRA_IO_PAD_LVDS,
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TEGRA_IO_PAD_MIPI_BIAS,
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TEGRA_IO_PAD_NAND,
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TEGRA_IO_PAD_PEX_BIAS,
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TEGRA_IO_PAD_PEX_CLK1,
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TEGRA_IO_PAD_PEX_CLK2,
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TEGRA_IO_PAD_PEX_CNTRL,
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TEGRA_IO_PAD_SDMMC1,
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TEGRA_IO_PAD_SDMMC3,
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TEGRA_IO_PAD_SDMMC4,
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TEGRA_IO_PAD_SPI,
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TEGRA_IO_PAD_SPI_HV,
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TEGRA_IO_PAD_SYS_DDC,
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TEGRA_IO_PAD_UART,
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TEGRA_IO_PAD_USB0,
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TEGRA_IO_PAD_USB1,
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TEGRA_IO_PAD_USB2,
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TEGRA_IO_PAD_USB3,
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TEGRA_IO_PAD_USB_BIAS,
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};
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/* deprecated, use TEGRA_IO_PAD_{HDMI,LVDS} instead */
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#define TEGRA_IO_RAIL_HDMI TEGRA_IO_PAD_HDMI
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#define TEGRA_IO_RAIL_LVDS TEGRA_IO_PAD_LVDS
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/**
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* enum tegra_io_pad_voltage - voltage level of the I/O pad's source rail
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* @TEGRA_IO_PAD_1800000UV: 1.8 V
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* @TEGRA_IO_PAD_3300000UV: 3.3 V
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*/
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enum tegra_io_pad_voltage {
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TEGRA_IO_PAD_1800000UV,
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TEGRA_IO_PAD_3300000UV,
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};
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#ifdef CONFIG_ARCH_TEGRA
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int tegra_powergate_is_powered(unsigned int id);
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int tegra_powergate_power_on(unsigned int id);
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int tegra_powergate_power_off(unsigned int id);
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int tegra_powergate_remove_clamping(unsigned int id);
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/* Must be called with clk disabled, and returns with clk enabled */
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int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
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struct reset_control *rst);
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int tegra_io_pad_power_enable(enum tegra_io_pad id);
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int tegra_io_pad_power_disable(enum tegra_io_pad id);
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int tegra_io_pad_set_voltage(enum tegra_io_pad id,
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enum tegra_io_pad_voltage voltage);
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int tegra_io_pad_get_voltage(enum tegra_io_pad id);
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/* deprecated, use tegra_io_pad_power_{enable,disable}() instead */
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int tegra_io_rail_power_on(unsigned int id);
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int tegra_io_rail_power_off(unsigned int id);
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#else
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static inline int tegra_powergate_is_powered(unsigned int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_power_on(unsigned int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_power_off(unsigned int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_remove_clamping(unsigned int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_powergate_sequence_power_up(unsigned int id,
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struct clk *clk,
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struct reset_control *rst)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_pad_power_enable(enum tegra_io_pad id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_pad_power_disable(enum tegra_io_pad id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_pad_set_voltage(enum tegra_io_pad id,
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enum tegra_io_pad_voltage voltage)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_pad_get_voltage(enum tegra_io_pad id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_rail_power_on(unsigned int id)
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{
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return -ENOSYS;
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}
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static inline int tegra_io_rail_power_off(unsigned int id)
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{
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return -ENOSYS;
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}
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#endif /* CONFIG_ARCH_TEGRA */
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#endif /* __SOC_TEGRA_PMC_H__ */
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