From 185ea867eb145905cbfaf1d57fe6ecb959805d84 Mon Sep 17 00:00:00 2001
From: "Mikhail R. Gadelha" <mikhail@igalia.com>
Date: Thu, 16 Mar 2023 13:24:22 -0300
Subject: [PATCH] [RISCV] Fix missing addi in test to validate lower inline asm
 m with offset

---
 llvm/test/CodeGen/RISCV/inline-asm.ll | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/llvm/test/CodeGen/RISCV/inline-asm.ll b/llvm/test/CodeGen/RISCV/inline-asm.ll
index ba78d722a16d..22d382517ccd 100644
--- a/llvm/test/CodeGen/RISCV/inline-asm.ll
+++ b/llvm/test/CodeGen/RISCV/inline-asm.ll
@@ -93,6 +93,8 @@ define i32 @constraint_m_with_offset(ptr %a) nounwind {
 ;
 ; RV64I-LABEL: constraint_m_with_offset:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a0, a0, 4
+; RV64I-NEXT:    #APP
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    #NO_APP
 ; RV64I-NEXT:    ret