[ARM] Remove a redundant function fixupBTI
Since the redundant BTI instructions emitted by jump tables are now removed in the ARMBranchTargets pass, the fixupBTI function is not needed in the ARMConstantIslandPass. Some related tests are removed as well. The relevant patch that removes the redundant BTI instructions: https://reviews.llvm.org/D144470 Differential Revision: https://reviews.llvm.org/D145048
This commit is contained in:
Jirui Wu
parent
ed05dcc57b
commit
3b742242a5
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@ -277,8 +277,6 @@ namespace {
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unsigned &DeadSize, bool &CanDeleteLEA,
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bool &BaseRegKill);
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bool optimizeThumb2JumpTables();
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void fixupBTI(unsigned JTI, MachineBasicBlock &OldBB,
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MachineBasicBlock &NewBB);
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MachineBasicBlock *adjustJTTargetBlockForward(unsigned JTI,
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MachineBasicBlock *BB,
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MachineBasicBlock *JTBB);
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@ -2455,38 +2453,6 @@ bool ARMConstantIslands::reorderThumb2JumpTables() {
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return MadeChange;
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}
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void ARMConstantIslands::fixupBTI(unsigned JTI, MachineBasicBlock &OldBB,
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MachineBasicBlock &NewBB) {
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assert(isThumb2 && "BTI in Thumb1?");
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// Insert a BTI instruction into NewBB
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BuildMI(NewBB, NewBB.begin(), DebugLoc(), TII->get(ARM::t2BTI));
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// Update jump table reference counts.
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const MachineJumpTableInfo &MJTI = *MF->getJumpTableInfo();
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const MachineJumpTableEntry &JTE = MJTI.getJumpTables()[JTI];
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for (const MachineBasicBlock *MBB : JTE.MBBs) {
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if (MBB != &OldBB)
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continue;
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--BlockJumpTableRefCount[MBB];
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++BlockJumpTableRefCount[&NewBB];
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}
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// If the old basic block reference count dropped to zero, remove
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// the BTI instruction at its beginning.
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if (BlockJumpTableRefCount[&OldBB] > 0)
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return;
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// Skip meta instructions
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auto BTIPos = llvm::find_if_not(OldBB.instrs(), [](const MachineInstr &MI) {
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return MI.isMetaInstruction();
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});
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assert(BTIPos->getOpcode() == ARM::t2BTI &&
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"BasicBlock is mentioned in a jump table but does start with BTI");
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if (BTIPos->getOpcode() == ARM::t2BTI)
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BTIPos->eraseFromParent();
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}
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MachineBasicBlock *ARMConstantIslands::adjustJTTargetBlockForward(
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unsigned JTI, MachineBasicBlock *BB, MachineBasicBlock *JTBB) {
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// If the destination block is terminated by an unconditional branch,
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@ -2546,9 +2512,6 @@ MachineBasicBlock *ARMConstantIslands::adjustJTTargetBlockForward(
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NewBB->addSuccessor(BB);
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JTBB->replaceSuccessor(BB, NewBB);
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if (MF->getInfo<ARMFunctionInfo>()->branchTargetEnforcement())
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fixupBTI(JTI, *BB, *NewBB);
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++NumJTInserted;
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return NewBB;
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}
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@ -1,311 +0,0 @@
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# RUN: llc -verify-machineinstrs -run-pass arm-cp-islands %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-unknown-eabi"
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; Tests adjustments to jump tables, made by the ARM Constant Islands pass
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; int g(int), h(int);
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; void g0(int), g1(int), g2(int);
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; void h0(int), h1(int), h2(int);
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;
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; void f(int x) {
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; for (;;) {
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; up:
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; x = g(x);
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; switch (x) {
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; case 0:
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; g0(x);
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; break;
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; case 1:
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; g1(x);
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; break;
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; case 2:
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; g2(x);
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; break;
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; case 3:
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; break;
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; case 4:
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; for (;;) {
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; x = h(x);
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; switch (x) {
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; case 0:
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; h0(x);
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; break;
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; case 1:
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; h1(x);
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; break;
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; case 2:
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; h2(x);
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; break;
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; case 3:
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; goto up;
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; case 4:
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; return;
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; }
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; }
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; }
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; }
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; }
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define hidden void @f(i32 %x) local_unnamed_addr #0 {
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entry:
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br label %up
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up: ; preds = %up, %sw.bb, %sw.bb1, %sw.bb2, %up.backedge.loopexit, %entry
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%x.addr.1 = phi i32 [ %x, %entry ], [ %call, %up ], [ %call, %sw.bb2 ], [ %call, %sw.bb1 ], [ %call, %sw.bb ], [ %call5, %up.backedge.loopexit ]
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%call = tail call i32 @g(i32 %x.addr.1)
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switch i32 %call, label %up [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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i32 4, label %for.cond4.preheader
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]
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for.cond4.preheader: ; preds = %up
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br label %for.cond4
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up.backedge.loopexit: ; preds = %for.cond4
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br label %up
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sw.bb: ; preds = %up
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tail call void @g0(i32 0)
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br label %up
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sw.bb1: ; preds = %up
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tail call void @g1(i32 1)
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br label %up
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sw.bb2: ; preds = %up
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tail call void @g2(i32 2)
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br label %up
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for.cond4: ; preds = %for.cond4, %sw.bb6, %sw.bb7, %sw.bb8, %for.cond4.preheader
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%x.addr.2 = phi i32 [ %call, %for.cond4.preheader ], [ %call5, %sw.bb8 ], [ %call5, %sw.bb7 ], [ %call5, %sw.bb6 ], [ %call5, %for.cond4 ]
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%call5 = tail call i32 @h(i32 %x.addr.2)
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switch i32 %call5, label %for.cond4 [
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i32 0, label %sw.bb6
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i32 1, label %sw.bb7
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i32 2, label %sw.bb8
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i32 3, label %up.backedge.loopexit
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i32 4, label %sw.bb10
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]
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sw.bb6: ; preds = %for.cond4
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tail call void @h0(i32 0)
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br label %for.cond4
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sw.bb7: ; preds = %for.cond4
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tail call void @h1(i32 1)
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br label %for.cond4
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sw.bb8: ; preds = %for.cond4
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tail call void @h2(i32 2)
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br label %for.cond4
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sw.bb10: ; preds = %for.cond4
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ret void
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}
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declare dso_local i32 @g(i32)
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declare dso_local void @g0(i32)
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declare dso_local void @g1(i32)
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declare dso_local void @g2(i32)
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declare dso_local i32 @h(i32)
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declare dso_local void @h0(i32)
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declare dso_local void @h1(i32)
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declare dso_local void @h2(i32)
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attributes #0 = { nounwind "disable-tail-calls"="false" "frame-pointer"="none" "no-jump-tables"="false" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+fp-armv8d16sp,+fp16,+fullfp16,+hwdiv,+lob,+ras,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 8, !"branch-target-enforcement", i32 1}
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...
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---
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name: f
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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debugValueSubstitutions: []
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constants: []
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machineFunctionInfo: {}
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jumpTable:
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kind: inline
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entries:
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- id: 0
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blocks: [ '%bb.3', '%bb.4', '%bb.5', '%bb.1', '%bb.7' ]
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- id: 1
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blocks: [ '%bb.6', '%bb.9', '%bb.10', '%bb.1', '%bb.11' ]
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# %bb.4 and %bb.10 redirect to %bb1, the rest are just renumbered
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# CHECK-LABEL: jumpTable:
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# CHECK-NEXT: kind: inline
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# CHECK-NEXT: entries:
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# CHECK-NEXT: - id: 0
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# CHECK-NEXT: blocks: [ '%bb.6', '%bb.14', '%bb.5', '%bb.4', '%bb.7' ]
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# CHECK-NEXT: - id: 1
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# CHECK-NEXT: blocks: [ '%bb.11', '%bb.12', '%bb.13', '%bb.10', '%bb.15' ]
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# %bb.1 loses the BTI
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# CHECK-LABEL: bb.1.up (align 4):
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# CHECK-NOT: t2BTI
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# CHECK-LABEL: bb.2.up:
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# CHECK-LABEL: bb.4.up:
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# CHECK: t2BTI
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# CHECK: tB %bb.1
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# CHECK-LABEL: bb.10.for.cond4:
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# CHECK: t2BTI
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# CHECK: tB %bb.1
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body: |
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bb.0.entry:
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successors: %bb.1(0x80000000)
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liveins: $r0, $r4, $lr
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t2BTI
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frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r4, -8
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$r4 = tMOVr killed $r0, 14 /* CC::al */, $noreg
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t2B %bb.1, 14 /* CC::al */, $noreg
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bb.5.sw.bb2:
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successors: %bb.1(0x80000000)
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liveins: $r4
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t2BTI
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$r0, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @g2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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bb.1.up (align 4):
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successors: %bb.1(0x20000000), %bb.2(0x60000000)
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liveins: $r4
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t2BTI
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$r0 = tMOVr killed $r4, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @g, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
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$r4 = tMOVr $r0, 14 /* CC::al */, $noreg
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tCMPi8 killed $r0, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.1, 8 /* CC::hi */, killed $cpsr
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bb.2.up:
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successors: %bb.3(0x15555555), %bb.4(0x15555555), %bb.5(0x15555555), %bb.1(0x2aaaaaab), %bb.7(0x15555555)
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liveins: $r4
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renamable $r0 = t2LEApcrelJT %jump-table.0, 14 /* CC::al */, $noreg
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renamable $r0 = t2ADDrs killed renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
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t2BR_JT killed renamable $r0, renamable $r4, %jump-table.0
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bb.3.sw.bb:
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successors: %bb.1(0x80000000)
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liveins: $r4
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t2BTI
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$r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @g0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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t2B %bb.1, 14 /* CC::al */, $noreg
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bb.6.sw.bb6:
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successors: %bb.7(0x80000000)
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liveins: $r4
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t2BTI
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$r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @h0, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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bb.7.for.cond4 (align 4):
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successors: %bb.7(0x3efbefc0), %bb.8(0x41041040)
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liveins: $r4
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t2BTI
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$r0 = tMOVr killed $r4, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @h, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
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$r4 = tMOVr $r0, 14 /* CC::al */, $noreg
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tCMPi8 killed $r0, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.7, 8 /* CC::hi */, killed $cpsr
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bb.8.for.cond4:
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successors: %bb.6(0x29555555), %bb.9(0x29555555), %bb.10(0x29555555), %bb.1(0x02000000), %bb.11(0x02000000)
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liveins: $r4
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renamable $r0 = t2LEApcrelJT %jump-table.1, 14 /* CC::al */, $noreg
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renamable $r0 = t2ADDrs killed renamable $r0, renamable $r4, 18, 14 /* CC::al */, $noreg, $noreg
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t2BR_JT killed renamable $r0, renamable $r4, %jump-table.1
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bb.9.sw.bb7:
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successors: %bb.7(0x80000000)
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liveins: $r4
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t2BTI
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$r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @h1, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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t2B %bb.7, 14 /* CC::al */, $noreg
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bb.10.sw.bb8:
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successors: %bb.7(0x80000000)
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liveins: $r4
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t2BTI
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$r0, dead $cpsr = tMOVi8 2, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @h2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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t2B %bb.7, 14 /* CC::al */, $noreg
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bb.4.sw.bb1:
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successors: %bb.1(0x80000000)
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liveins: $r4
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t2BTI
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$r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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tBL 14 /* CC::al */, $noreg, @g1, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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t2B %bb.1, 14 /* CC::al */, $noreg
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bb.11.sw.bb10:
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t2BTI
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r4, def $pc
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...
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@ -1,168 +0,0 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv7m-arm-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
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# This test checks that the ARM Constant Island pass correctly handles BTI
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# instructions when adding new BBs to jump tables.
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#
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# Specifically the pass will replace bb.1.bb42.i in the jump table with a new
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# BB which will contain an unconditional branch to bb.1.bb42.i.
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# We expect that a BTI instruction will be added to the new BB and removed from
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# bb.1.bb42.i.
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--- |
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declare noalias ptr @calloc(i32, i32)
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define internal i32 @test(i32 %argc, ptr nocapture %argv) {
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entry:
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br label %bb42.i
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bb5.i:
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%0 = or i32 %argc, 32
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br label %bb42.i
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bb35.i:
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%1 = call noalias ptr @calloc(i32 20, i32 1)
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unreachable
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bb37.i:
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%2 = call noalias ptr @calloc(i32 14, i32 1)
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unreachable
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bb39.i:
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%3 = call noalias ptr @calloc(i32 17, i32 1)
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unreachable
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bb42.i:
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switch i32 %argc, label %bb39.i [
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i32 70, label %bb35.i
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i32 77, label %bb37.i
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i32 100, label %bb5.i
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i32 101, label %bb42.i
|
||||
i32 116, label %bb42.i
|
||||
]
|
||||
}
|
||||
|
||||
!llvm.module.flags = !{!0}
|
||||
!0 = !{i32 8, !"branch-target-enforcement", i32 1}
|
||||
|
||||
...
|
||||
---
|
||||
name: test
|
||||
alignment: 4
|
||||
tracksRegLiveness: true
|
||||
liveins:
|
||||
- { reg: '$r0' }
|
||||
frameInfo:
|
||||
stackSize: 8
|
||||
maxAlignment: 4
|
||||
adjustsStack: true
|
||||
hasCalls: true
|
||||
maxCallFrameSize: 0
|
||||
stack:
|
||||
- { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr' }
|
||||
- { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
|
||||
machineFunctionInfo: {}
|
||||
jumpTable:
|
||||
kind: inline
|
||||
entries:
|
||||
- id: 0
|
||||
blocks: [ '%bb.3', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.5', '%bb.4', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.1', '%bb.1', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.5',
|
||||
'%bb.5', '%bb.5', '%bb.5', '%bb.5', '%bb.1' ]
|
||||
body: |
|
||||
; CHECK-LABEL: name: test
|
||||
; CHECK: bb.0.entry:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $r0, $r7, $lr
|
||||
; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 70, 14 /* CC::al */, $noreg
|
||||
; CHECK: bb.1.bb42.i (align 4):
|
||||
; CHECK: successors: %bb.6(0x40000000), %bb.2(0x40000000)
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: tCMPi8 renamable $r0, 46, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
; CHECK: tBcc %bb.6, 8 /* CC::hi */, killed $cpsr
|
||||
; CHECK: bb.2.bb42.i:
|
||||
; CHECK: successors: %bb.5(0x20000000), %bb.6(0x20000000), %bb.7(0x20000000), %bb.4(0x20000000)
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: t2TBB_JT $pc, $r0, %jump-table.0, 0
|
||||
; CHECK: bb.3:
|
||||
; CHECK: successors:
|
||||
; CHECK: JUMPTABLE_TBB 0, %jump-table.0, 188
|
||||
; CHECK: bb.4.bb42.i:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: liveins: $r0
|
||||
; CHECK: t2BTI
|
||||
; CHECK: tB %bb.1, 14 /* CC::al */, $noreg
|
||||
; CHECK: bb.5.bb35.i:
|
||||
; CHECK: successors:
|
||||
; CHECK: t2BTI
|
||||
; CHECK: $r0, dead $cpsr = tMOVi8 20, 14 /* CC::al */, $noreg
|
||||
; CHECK: $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
; CHECK: tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
|
||||
; CHECK: bb.6.bb39.i:
|
||||
; CHECK: successors:
|
||||
; CHECK: t2BTI
|
||||
; CHECK: $r0, dead $cpsr = tMOVi8 17, 14 /* CC::al */, $noreg
|
||||
; CHECK: $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
; CHECK: tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
|
||||
; CHECK: bb.7.bb37.i:
|
||||
; CHECK: t2BTI
|
||||
; CHECK: $r0, dead $cpsr = tMOVi8 14, 14 /* CC::al */, $noreg
|
||||
; CHECK: $r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
; CHECK: tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
|
||||
bb.0.entry:
|
||||
liveins: $r0, $r7, $lr
|
||||
|
||||
frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 8
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 70, 14 /* CC::al */, $noreg
|
||||
|
||||
bb.1.bb42.i (align 4):
|
||||
successors: %bb.5, %bb.2
|
||||
liveins: $r0
|
||||
|
||||
t2BTI
|
||||
tCMPi8 renamable $r0, 46, 14 /* CC::al */, $noreg, implicit-def $cpsr
|
||||
t2Bcc %bb.5, 8 /* CC::hi */, killed $cpsr
|
||||
|
||||
bb.2.bb42.i:
|
||||
successors: %bb.3, %bb.5, %bb.4, %bb.1
|
||||
liveins: $r0
|
||||
|
||||
renamable $r1 = t2LEApcrelJT %jump-table.0, 14 /* CC::al */, $noreg
|
||||
renamable $r1 = t2ADDrs killed renamable $r1, renamable $r0, 18, 14 /* CC::al */, $noreg, $noreg
|
||||
t2BR_JT killed renamable $r1, renamable $r0, %jump-table.0
|
||||
|
||||
bb.3.bb35.i:
|
||||
successors:
|
||||
|
||||
t2BTI
|
||||
$r0, dead $cpsr = tMOVi8 20, 14 /* CC::al */, $noreg
|
||||
$r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
|
||||
|
||||
bb.5.bb39.i:
|
||||
successors:
|
||||
|
||||
t2BTI
|
||||
$r0, dead $cpsr = tMOVi8 17, 14 /* CC::al */, $noreg
|
||||
$r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
|
||||
|
||||
bb.4.bb37.i:
|
||||
t2BTI
|
||||
$r0, dead $cpsr = tMOVi8 14, 14 /* CC::al */, $noreg
|
||||
$r1, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
|
||||
tBL 14 /* CC::al */, $noreg, @calloc, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def dead $r0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user