Commit Graph

426514 Commits

Author SHA1 Message Date
Guillaume Chatelet
01a8b89edb [NFC][Alignment] Use getAlign in ARMFastISel 2022-06-13 13:36:36 +00:00
Nikita Popov
b9a7dea917 [SelectionDAG] Handle trapping aggregate (PR49839)
Call canTrap() on Constant to account for trapping
ConstantAggregate.
2022-06-13 15:06:53 +02:00
Nikita Popov
483a4b2226 [SelectionDAG] Add test for PR49839 (NFC) 2022-06-13 15:06:53 +02:00
Guillaume Chatelet
86f455750b [NFC] Remove dead code 2022-06-13 12:59:38 +00:00
Guillaume Chatelet
eeda07e14b [NFC][Alignment] Use proper type in tests 2022-06-13 12:59:38 +00:00
Guillaume Chatelet
a6c2ab0c3f [NFC][Alignment] Use proper type in instrumentLoadOrStore 2022-06-13 12:59:38 +00:00
Guillaume Chatelet
d1a27d0b9c [NFC][Alignment] Use proper version of getAlign 2022-06-13 12:59:38 +00:00
Guillaume Chatelet
40109fa101 [NFC][Alignment] Use proper type in LLVMGetAlignment 2022-06-13 12:59:37 +00:00
Nikita Popov
571c713144 [SimplifyCFG] Handle trapping aggregates (PR49839)
Handle the fact that not only constant expressions, but also
constant aggregates containing expressions can trap.

This still doesn't fix the original C reproducer, probably due to
more issues remaining in other passes.
2022-06-13 14:56:49 +02:00
Amaury Séchet
9ecf423453 [AArch64] Autogenerate sve-fixed-length tests. NFC
As per title. This makes it easier to work onc hange that require "shotgun diffs" over the codebase.

Reviewed By: paulwalker-arm

Differential Revision: https://reviews.llvm.org/D127118
2022-06-13 12:50:07 +00:00
Vladislav Khmelevsky
6e26ffa064 [BOLT][AARCH64] Skip R_AARCH64_LD_PREL_LO19 relocation
Supress failed to analyze relocations warning for R_AARCH64_LD_PREL_LO19
relocation. This relocation is mostly used to get value stored in CI and
we don't process it since we are caluclating target address using the
instruction value in evaluateMemOperandTarget().

Differential Revision: https://reviews.llvm.org/D127413
2022-06-13 15:40:06 +03:00
wangpc
93b4a41b55 [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h
These two functions are described in RVV intrinsics doc
to read/write RVV CSRs. This matches what GCC does.

This reapply aebe24a which was reverted in 0f6f429 due
to missing REQUIRES in tests.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125875
2022-06-13 20:38:52 +08:00
Jay Foad
438c312c03 [AMDGPU] Add GFX11 flat scratch test coverage 2022-06-13 13:38:12 +01:00
Nikita Popov
abefed6f97 [SimplifyCFG] Add test for PR49839 (NFC) 2022-06-13 14:35:09 +02:00
Benjamin Kramer
5724231af2 [InstCombine] Only fold trunc(ext) pairs to bitcast if the source and destination types are the same
This used to be always the case, but the addition of bfloat to the type
matrix makes this invalid.
2022-06-13 14:34:18 +02:00
Frederik Gossen
ff6ce9e8fc Add createDynamicDimValues to tensor dialect utils
The function creates dim ops for each dynamic dimension of the raked tensor
argument and returns these as values.

Differential Revision: https://reviews.llvm.org/D127533
2022-06-13 08:26:28 -04:00
Valentin Clement
a405db9c37
[flang][NFC] Fix typo 2022-06-13 14:19:45 +02:00
LLVM GN Syncbot
5a0ec6ff68 [gn build] Port e183bf8e15 2022-06-13 12:03:48 +00:00
Jan Svoboda
2de36d0369 [clang][driver] Only run multi-arch tests on Darwin
This fixes the test introduced in a85670001b that causes failures on non-Darwin systems.
2022-06-13 14:03:23 +02:00
Jez Ng
b422dac240 [lld-macho][reland] Support EH frames under arm64
This reverts commit 10641a42e2.

Differential Revision: https://reviews.llvm.org/D124561
2022-06-13 07:45:27 -04:00
Jez Ng
e183bf8e15 [lld-macho][reland] Initial support for EH Frames
This reverts commit 942f4e3a7c.

The additional change required to avoid the assertion errors seen
previously is:

  --- a/lld/MachO/ICF.cpp
  +++ b/lld/MachO/ICF.cpp
  @@ -443,7 +443,9 @@ void macho::foldIdenticalSections() {
                                 /*relocVA=*/0);
           isec->data = copy;
         }
  -    } else {
  +    } else if (!isEhFrameSection(isec)) {
  +      // EH frames are gathered as hashables from unwindEntry above; give a
  +      // unique ID to everything else.
         isec->icfEqClass[0] = ++icfUniqueID;
       }
     }

Differential Revision: https://reviews.llvm.org/D123435
2022-06-13 07:45:16 -04:00
Jez Ng
e4a21e1644 [MC] Fix likely uninitialized memory bug
See https://reviews.llvm.org/D122258#inline-1223493. I can't repro the
issue locally but this seems like the likely culprit.

Reviewed By: uabelho

Differential Revision: https://reviews.llvm.org/D127630
2022-06-13 07:41:17 -04:00
wangpc
0f6f4295d1 Revert "[RISCV] Add vread_csr and vwrite_csr to riscv_vector.h"
This reverts commit aebe24a856.

`REQUIRES` for RISCV target is needed in tests.
2022-06-13 19:31:25 +08:00
Jan Svoboda
a85670001b [clang][driver] Fix compilation database dump with multiple architectures
Command lines with multiple `-arch` arguments expand into multiple entries in the compilation database. However, the file writes are not appending, meaning subsequent writes end up overwriting the previous ones, resulting in garbled output.

This patch fixes that by always appending to the file.

rdar://90165004

Reviewed By: dexonsmith

Differential Revision: https://reviews.llvm.org/D121997
2022-06-13 13:30:57 +02:00
Jan Svoboda
c12577c61d [clang][driver] Introduce new -fdriver-only flag
This patch introduces the new -fdriver-only flag which instructs Clang to only execute the driver logic without running individual jobs. In a way, this is very similar to -###, with the following differences:
 * it doesn't automatically print all jobs,
 * it doesn't avoid side effects (e.g. it will generate compilation database when -MJ is specified).

This flag will be useful in testing D121997.

Reviewed By: dexonsmith, egorzhdan

Differential Revision: https://reviews.llvm.org/D127408
2022-06-13 13:30:56 +02:00
Mats Petersson
84b9ae6624 [flang]Add support for do concurrent
[flang]Add support for do concurrent

Upstreaming from fir-dev on https://github.com/flang-compiler/f18-llvm-project

Support for concurrent execution in do-loops.

A selection of tests are also added.

Co-authored-by: V Donaldson <vdonaldson@nvidia.com>

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D127240
2022-06-13 12:28:49 +01:00
wangpc
aebe24a856 [RISCV] Add vread_csr and vwrite_csr to riscv_vector.h
These two functions are described in RVV intrinsics doc
to read/write RVV CSRs. This matches what GCC does.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D125875
2022-06-13 19:12:15 +08:00
Simon Pilgrim
7d8fd4f5db [DAG] visitINSERT_VECTOR_ELT - attempt to reconstruct BUILD_VECTOR before other fold interfere
Another issue unearthed by D127115

We take a long time to canonicalize an insert_vector_elt chain before being able to convert it into a build_vector - even if they are already in ascending insertion order, we fold the nodes one at a time into the build_vector 'seed', leaving plenty of time for other folds to alter it (in particular recognising when they come from extract_vector_elt resulting in a shuffle_vector that is much harder to fold with).

D127115 makes this particularly difficult as we're almost guaranteed to have the lost the sequence before all possible insertions have been folded.

This patch proposes to begin at the last insertion and attempt to collect all the (oneuse) insertions right away and create the build_vector before its too late.

Differential Revision: https://reviews.llvm.org/D127595
2022-06-13 11:48:18 +01:00
Simon Pilgrim
f97e15ef45 [ARM] Fix "local variable is initialized but not referenced" MSVX warning. NFC 2022-06-13 11:48:06 +01:00
zhongyunde
3cefcdb8c6 [test] Add test for D126700 NFC 2022-06-13 18:37:29 +08:00
Nikita Popov
7e64a29e58 [InstSimplify][IR] Handle trapping constant aggregate (PR49839)
Unfortunately, it's not just constant expressions that can trap,
we might also have a trapping constant expression nested inside
a constant aggregate.

Perform the check during phi folding on Constant rather than
ConstantExpr, and extend the Constant::mayTrap() implementation
to also recursive into ConstantAggregates, not just ConstantExprs.

Fixes https://github.com/llvm/llvm-project/issues/49839.
2022-06-13 12:35:17 +02:00
LLVM GN Syncbot
d59809de16 [gn build] Port 988682a389 2022-06-13 10:23:45 +00:00
Nikita Popov
c232a15df4 [InstSimplify] Add additional test for PR49839 (NFC)
This is a variant involving an aggregate constant, which was not
covered by the previous patch.
2022-06-13 12:23:30 +02:00
David Truby
b4f2f7bebd [clang][AArch64][SVE] Implicit conversions for vector-scalar operations
This patch allows the same implicit conversions for vector-scalar
operations in SVE that are allowed for NEON.

Depends on D126377

Reviewed By: c-rhodes

Differential Revision: https://reviews.llvm.org/D126380
2022-06-13 10:22:10 +00:00
Nikolas Klauser
988682a389 [libc++] Fix std::lower_bound with C++20-hostile iterators
Reviewed By: EricWF, #libc

Spies: sstefan1, libcxx-commits, mgorny

Differential Revision: https://reviews.llvm.org/D127577
2022-06-13 12:19:28 +02:00
Guillaume Chatelet
f9bb8c24ac [NFC][Alignment] Convert MemCpyOptimizer.cpp 2022-06-13 10:07:09 +00:00
Lucas Prates
33b9ad647e Revert "[ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records"
Reverting change due to test failure.

This reverts commit 6119053dab.
2022-06-13 11:00:49 +01:00
David Sherwood
83251896d7 [NFC][InstCombine] Refactor InstCombinerImpl::foldSelectIntoOp
Introduce a lambda function so that we remove a lot of code
duplication.

Differential Revision: https://reviews.llvm.org/D127493
2022-06-13 10:37:07 +01:00
zhongyunde
c42a225545 [MachineScheduler] Order more stores by ascending address
According D125377, we order STP Q's by ascending address. While on some
targets, paired 128 bit loads and stores are slow, so the STP will split
into STRQ and STUR, so I hope these stores will also be ordered.
Also add subtarget feature ascend-store-address to control the aggressive order.

Reviewed By: dmgreen, fhahn

Differential Revision: https://reviews.llvm.org/D126700
2022-06-13 17:33:50 +08:00
Lucas Prates
6119053dab [ARM][Thumb] Command-line option to ensure AAPCS compliant Frame Records
Currently the a AAPCS compliant frame record is not always created for
functions when it should. Although a consistent frame record might not
be required in some cases, there are still scenarios where applications
may want to make use of the call hierarchy made available trough it.

In order to enable the use of AAPCS compliant frame records whilst keep
backwards compatibility, this patch introduces a new command-line option
(`-mframe-chain=[none|aapcs|aapcs+leaf]`) for Aarch32 and Thumb backends.
The option allows users to explicitly select when to use it, and is also
useful to ensure the extra overhead introduced by the frame records is
only introduced when necessary, in particular for Thumb targets.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D125094
2022-06-13 10:21:06 +01:00
Lucas Prates
7775124b5c [NFC][Thumb1] Use FrameDestroy flag to identify epilog instructions
Simiarly to what's done on both ARM's and AArch64's frame lowering code,
this updates Thumb1FrameLowering to use the FrameDestroy Machine
Instruction flag to identify instructions inserted as part of the epilog
instead of relying on assumptions about specific machine instructions.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D126285
2022-06-13 10:19:10 +01:00
Adrian Kuegel
8ab925a2fd [mlir] Fix ClangTidyPerformance finding (NFC). 2022-06-13 10:49:25 +02:00
Nikita Popov
92a9b1c918 [InstCombine] Don't push operation across loop phi
When pushing an operation across a phi node, we should avoid doing
so across a loop backedge. This is generally non-profitable, because
it does not reduce the number of times the operation is executed,
and could lead to an infinite combine loop.

The code was already guarding against this, but using an
insufficiently strong condition, which did not cover the case where
the operation was originally outside the loop (in which case the
transform moves the operation from outside the loop into the loop,
which is particularly undesirable).

Differential Revision: https://reviews.llvm.org/D127499
2022-06-13 10:48:09 +02:00
Nikita Popov
2a3288776c [InstSimplify] Update GEP test to use opaque pointers (NFC)
With opaque pointers, we end up merging these GEPs and dropping
the inrange attribute (in the last two cases). This did not happen
previously, because typed pointers use less powerful GEP folding logic.

I'm a bit unsure whether this is something we need to be concerned
about or not. I believe that generally our stance is that we should
perform folds even if this requires losing poison-generating flags
like inrange.

We can either a) accept this as-is, b) try to inhibit folding if it
requires dropping inrange or c) try to fold to poison if we know
that inrange is going to be violated.

For now, we accept it as-is.

Differential Revision: https://reviews.llvm.org/D127503
2022-06-13 10:45:55 +02:00
David Green
dbac0e83d1 [AArch64] Mark smull and umull as commutative. 2022-06-13 09:24:15 +01:00
Nuno Lopes
5a132499fb [NFC] Remove straight UB from SROA tests
Including 'br undef', store/load to undef pointers.
Plus some cosmetics: select undef, insertvalue undef -> poison.

Recommit c1b6103 with fix.
2022-06-13 08:59:07 +01:00
Guillaume Chatelet
6e930503f4 [NFC][polly] Removed dead code 2022-06-13 07:50:35 +00:00
Maksim Panchenko
8f6512fea0 [X86][Disassembler] Fix displacement operand size for symbolizer
On 64-bit X86, 0x66 operand-size override prefix will change the size of
the instruction operand, e.g. from 32 bits to 16 bits, but it will not
modify the size of the displacement operand used for memory addressing,
which will always be 32 bits.

Reviewed By: skan, rafauler

Differential Revision: https://reviews.llvm.org/D126726
2022-06-13 00:14:43 -07:00
owenca
b1c300fe68 [clang-format] Handle deprecated options in dump_format_style.py
Also add two deprecated options as comments back to Format.h.
2022-06-12 23:35:48 -07:00
Fangrui Song
16ca490f45 [ELF] Change getRISCVPCRelHi20 error to conventional errorOrWarn 2022-06-12 21:15:06 -07:00