9d8a7f780c
Normally, the ISD::SELECT is lowered to maskeqz + masknez. This is inefficient when operands are constants that can be computed easily. To avoid that, override TargetLowering::convertSelectOfConstantsToMath. Differential Revision: https://reviews.llvm.org/D143621
265 lines
9.8 KiB
C++
265 lines
9.8 KiB
C++
//=- LoongArchISelLowering.h - LoongArch DAG Lowering Interface -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that LoongArch uses to lower LLVM code into
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// a selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
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#define LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
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#include "LoongArch.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/TargetLowering.h"
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namespace llvm {
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class LoongArchSubtarget;
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struct LoongArchRegisterInfo;
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namespace LoongArchISD {
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enum NodeType : unsigned {
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FIRST_NUMBER = ISD::BUILTIN_OP_END,
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// TODO: add more LoongArchISDs
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CALL,
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RET,
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TAIL,
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// 32-bit shifts, directly matching the semantics of the named LoongArch
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// instructions.
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SLL_W,
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SRA_W,
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SRL_W,
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ROTL_W,
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ROTR_W,
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// FPR<->GPR transfer operations
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MOVGR2FR_W_LA64,
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MOVFR2GR_S_LA64,
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MOVFCSR2GR,
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MOVGR2FCSR,
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FTINT,
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// Bit counting operations
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CLZ_W,
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CTZ_W,
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BSTRINS,
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BSTRPICK,
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// Byte-swapping and bit-reversal
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REVB_2H,
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REVB_2W,
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BITREV_4B,
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BITREV_W,
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// Intrinsic operations start ============================================
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BREAK,
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CACOP_D,
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CACOP_W,
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DBAR,
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IBAR,
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SYSCALL,
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// CRC check operations
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CRC_W_B_W,
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CRC_W_H_W,
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CRC_W_W_W,
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CRC_W_D_W,
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CRCC_W_B_W,
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CRCC_W_H_W,
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CRCC_W_W_W,
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CRCC_W_D_W,
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CSRRD,
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CSRWR,
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CSRXCHG,
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// IOCSR access operations
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IOCSRRD_B,
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IOCSRRD_W,
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IOCSRRD_H,
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IOCSRRD_D,
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IOCSRWR_B,
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IOCSRWR_H,
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IOCSRWR_W,
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IOCSRWR_D,
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// Read CPU configuration information operation
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CPUCFG,
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// Intrinsic operations end =============================================
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};
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} // end namespace LoongArchISD
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class LoongArchTargetLowering : public TargetLowering {
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const LoongArchSubtarget &Subtarget;
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public:
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explicit LoongArchTargetLowering(const TargetMachine &TM,
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const LoongArchSubtarget &STI);
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const LoongArchSubtarget &getSubtarget() const { return Subtarget; }
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bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
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// Provide custom lowering hooks for some operations.
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SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
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void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
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SelectionDAG &DAG) const override;
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SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
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// This method returns the name of a target specific DAG node.
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const char *getTargetNodeName(unsigned Opcode) const override;
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// Lower incoming arguments, copy physregs into vregs.
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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const SDLoc &DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
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bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const override;
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SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
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SelectionDAG &DAG) const override;
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SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const override;
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bool isCheapToSpeculateCttz(Type *Ty) const override;
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bool isCheapToSpeculateCtlz(Type *Ty) const override;
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bool hasAndNot(SDValue Y) const override;
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
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Value *emitMaskedAtomicRMWIntrinsic(IRBuilderBase &Builder, AtomicRMWInst *AI,
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Value *AlignedAddr, Value *Incr,
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Value *Mask, Value *ShiftAmt,
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AtomicOrdering Ord) const override;
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EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
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EVT VT) const override;
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TargetLowering::AtomicExpansionKind
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shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *CI) const override;
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Value *emitMaskedAtomicCmpXchgIntrinsic(IRBuilderBase &Builder,
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AtomicCmpXchgInst *CI,
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Value *AlignedAddr, Value *CmpVal,
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Value *NewVal, Value *Mask,
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AtomicOrdering Ord) const override;
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bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
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MachineFunction &MF,
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unsigned Intrinsic) const override;
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bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
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EVT VT) const override;
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Register
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getExceptionPointerRegister(const Constant *PersonalityFn) const override;
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Register
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getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
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ISD::NodeType getExtendForAtomicOps() const override {
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return ISD::SIGN_EXTEND;
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}
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Register getRegisterByName(const char *RegName, LLT VT,
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const MachineFunction &MF) const override;
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bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
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bool decomposeMulByConstant(LLVMContext &Context, EVT VT,
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SDValue C) const override;
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bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
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bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
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unsigned AS,
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Instruction *I = nullptr) const override;
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bool hasAndNotCompare(SDValue Y) const override;
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bool convertSelectOfConstantsToMath(EVT VT) const override { return true; }
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private:
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/// Target-specific function used to lower LoongArch calling conventions.
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typedef bool LoongArchCCAssignFn(const DataLayout &DL, LoongArchABI::ABI ABI,
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unsigned ValNo, MVT ValVT,
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CCValAssign::LocInfo LocInfo,
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ISD::ArgFlagsTy ArgFlags, CCState &State,
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bool IsFixed, bool IsReg, Type *OrigTy);
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void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
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const SmallVectorImpl<ISD::InputArg> &Ins, bool IsRet,
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LoongArchCCAssignFn Fn) const;
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void analyzeOutputArgs(MachineFunction &MF, CCState &CCInfo,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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bool IsRet, CallLoweringInfo *CLI,
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LoongArchCCAssignFn Fn) const;
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template <class NodeTy>
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SDValue getAddr(NodeTy *N, SelectionDAG &DAG, bool IsLocal = true) const;
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SDValue getStaticTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
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unsigned Opc) const;
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SDValue getDynamicTLSAddr(GlobalAddressSDNode *N, SelectionDAG &DAG,
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unsigned Opc) const;
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, bool IsSRA) const;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const override;
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SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerWRITE_REGISTER(SDValue Op, SelectionDAG &DAG) const;
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bool isFPImmLegal(const APFloat &Imm, EVT VT,
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bool ForCodeSize) const override;
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bool shouldInsertFencesForAtomic(const Instruction *I) const override;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const override;
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std::pair<unsigned, const TargetRegisterClass *>
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getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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StringRef Constraint, MVT VT) const override;
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void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
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std::vector<SDValue> &Ops,
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SelectionDAG &DAG) const override;
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bool isEligibleForTailCallOptimization(
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CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
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const SmallVectorImpl<CCValAssign> &ArgLocs) const;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHISELLOWERING_H
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