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AsmParser
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[RISCV] Improve validation of opcode for .insn.
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2023-03-21 16:20:30 -07:00 |
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Disassembler
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[RISCV] Add vendor-defined XTheadCondMov (conditional move) extension
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2023-02-24 21:40:42 +01:00 |
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GISel
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MCA
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MCTargetDesc
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[RISCV][MC] Adjust conditions to emit R_RISCV_ADD*/R_RISCV_SUB* pairs
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2023-03-14 15:17:38 -07:00 |
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TargetInfo
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CMakeLists.txt
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[RISCV] Add new pass to transform undef to pseudo for vector values.
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2023-02-22 04:03:22 -08:00 |
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RISCV.h
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[RISCV] Add new pass to transform undef to pseudo for vector values.
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2023-02-22 04:03:22 -08:00 |
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RISCV.td
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RISCVAsmPrinter.cpp
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[RISCV][MC][NFC] Refactor RISCVAsmPrinter::PrintAsmMemoryOperand to use early return
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2023-03-16 15:02:53 +00:00 |
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RISCVCallingConv.td
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RISCVCodeGenPrepare.cpp
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RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
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RISCVFeatures.td
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[Target][RISCV] Update SubtargetFeature definition for RV32/RV64 (NFCI).
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2023-03-17 08:49:45 +01:00 |
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RISCVFrameLowering.cpp
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[codegen][riscv] Emit CFI directives when using shadow call stack
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2023-03-15 17:10:23 +00:00 |
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RISCVFrameLowering.h
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RISCVGatherScatterLowering.cpp
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RISCVInsertVSETVLI.cpp
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RISCVInstrFormats.td
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[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
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2023-02-15 13:03:31 -08:00 |
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RISCVInstrFormatsC.td
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[RISCV] Remove 'rs1' field from RVInst16 class. NFC
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2023-03-21 14:58:53 -07:00 |
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RISCVInstrFormatsV.td
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RISCVInstrInfo.cpp
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[NFC][Outliner] Delete default ctors for Candidate & OutlinedFunction.
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2023-03-20 11:17:10 -07:00 |
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RISCVInstrInfo.h
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[NFC][Outliner] Delete default ctors for Candidate & OutlinedFunction.
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2023-03-20 11:17:10 -07:00 |
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RISCVInstrInfo.td
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[RISCV] Use LBU for extloadi8.
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2023-03-21 18:52:05 -07:00 |
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RISCVInstrInfoA.td
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[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.
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2023-02-25 20:07:41 -08:00 |
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RISCVInstrInfoC.td
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[RISCV][NFC] Add missing immediate operand types.
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2023-02-17 15:56:32 +03:00 |
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RISCVInstrInfoD.td
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[RISCV] Clear mayRaiseFPException for fclass.d instruction.
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2023-03-21 19:48:23 -07:00 |
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RISCVInstrInfoF.td
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[RISCV] Remove Commutable property from Zfa fltq/fleq instructions.
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2023-02-19 11:37:23 -08:00 |
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RISCVInstrInfoM.td
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RISCVInstrInfoV.td
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RISCVInstrInfoVPseudos.td
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[RISCV] Be more explicit string replacements in RISCVInstrInfoVPseudos.td. NFC
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2023-02-22 12:56:16 -08:00 |
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RISCVInstrInfoVSDPatterns.td
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[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
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2023-03-15 07:47:16 +08:00 |
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RISCVInstrInfoVVLPatterns.td
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[RISCV] Support ISD::STRICT_FADD/FSUB/FMUL/FDIV for vector types.
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2023-03-15 07:47:16 +08:00 |
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RISCVInstrInfoXTHead.td
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[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
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2023-02-25 12:05:48 -08:00 |
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RISCVInstrInfoXVentana.td
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[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
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2023-02-25 12:05:48 -08:00 |
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RISCVInstrInfoZb.td
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[RISCV] Add explicit i64 to reduce RISCVGenDAGISel.inc size.
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2023-02-25 10:07:26 -08:00 |
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RISCVInstrInfoZc.td
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[RISCV] Add CLB/CLH/SLB/SLH formats for Zcb instructions.
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2023-02-15 13:03:31 -08:00 |
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RISCVInstrInfoZfa.td
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[RISCV] Clear mayRaiseFPException for Zfa fmvh.x.d and fmvp.d.x instructions.
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2023-03-21 19:42:27 -07:00 |
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RISCVInstrInfoZfh.td
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[RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh
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2023-03-20 17:05:48 +00:00 |
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RISCVInstrInfoZicbo.td
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RISCVInstrInfoZk.td
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RISCVISelDAGToDAG.cpp
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[RISCV] Move fli selection in RISCVISelDAGToDAG.cpp. NFC
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2023-03-21 19:33:27 -07:00 |
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RISCVISelDAGToDAG.h
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[RISCV] Reuse the condop/invcondop ComplexPatterns for seteq/setne isel. NFC NFC NFC NFC
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2023-02-25 12:05:48 -08:00 |
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RISCVISelLowering.cpp
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[RISCV] Move fli selection in RISCVISelDAGToDAG.cpp. NFC
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2023-03-21 19:33:27 -07:00 |
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RISCVISelLowering.h
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[RISCV] Move fli selection in RISCVISelDAGToDAG.cpp. NFC
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2023-03-21 19:33:27 -07:00 |
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RISCVMachineFunctionInfo.cpp
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RISCVMachineFunctionInfo.h
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RISCVMacroFusion.cpp
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RISCVMacroFusion.h
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RISCVMakeCompressible.cpp
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RISCVMCInstLower.cpp
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RISCVMergeBaseOffset.cpp
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RISCVProcessors.td
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RISCVRedundantCopyElimination.cpp
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RISCVRegisterInfo.cpp
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RISCVRegisterInfo.h
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RISCVRegisterInfo.td
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RISCVRVVInitUndef.cpp
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[RISCV] Add new pass to transform undef to pseudo for vector values.
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2023-02-22 04:03:22 -08:00 |
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RISCVSchedRocket.td
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RISCVSchedSiFive7.td
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RISCVSchedSyntacoreSCR1.td
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RISCVSchedule.td
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RISCVScheduleV.td
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[RISCV] Add classes to define SchedWrite list
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2023-03-07 17:54:05 +08:00 |
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RISCVScheduleZb.td
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RISCVSExtWRemoval.cpp
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RISCVStripWSuffix.cpp
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[RISCV] Add MULW to RISCVStripWSuffix.
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2023-03-16 19:42:33 -07:00 |
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RISCVSubtarget.cpp
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[RISCV] Enable subregister liveness by default
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2023-03-08 23:03:35 -08:00 |
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RISCVSubtarget.h
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[Target][RISCV] Update SubtargetFeature definition for RV32/RV64 (NFCI).
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2023-03-17 08:49:45 +01:00 |
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RISCVSystemOperands.td
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RISCVTargetMachine.cpp
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[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation
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2023-03-14 17:55:11 +00:00 |
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RISCVTargetMachine.h
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RISCVTargetObjectFile.cpp
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[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
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2023-02-23 01:26:27 +00:00 |
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
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[RISCV] Enable interleaved access vectorization
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2023-03-16 15:48:55 +00:00 |
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RISCVTargetTransformInfo.h
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[RISCV] Enable interleaved access vectorization
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2023-03-16 15:48:55 +00:00 |
