This commit is contained in:
uziel 2024-11-08 14:50:39 +08:00
commit 0becdf3742
19 changed files with 43459 additions and 0 deletions

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.gitignore vendored Normal file
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images/rootfs_tmp/
images/linux-5.15.0+-arm64.tar.gz
images/initrd.img
images/Image
images/uImage_*
images/system-top.dtb

25
Makefile Normal file
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all:
./build_kernel.sh c
./build.sh
./copy.sh
c:
./build_kernel.sh c
deb:
./build_kernel.sh deb
ubonly:
./build.sh c
./copy.sh
ram:
./build_kernel.sh
./build.sh 1 1
./copy.sh
menu:
./build_kernel.sh menu
mrproper:
./build_kernel.sh mrproper

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README.md Normal file
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# introduce
to build kernel easily.
check this project at same level to the "./tmp_kernel_5.15/" will be nice.
# command
- build_kernel.sh : build kernel
- c: compile only
- debs: make debs packages
- menu: open menuconfig
- @noargs: make targz-pkg
- build.sh : build boot.img
- build.shbuild a kernel-only img file;
- build.sh 1 build a ramdisk img file;
- build.sh 1 1build a ramdisk img file with modules update
- copy.sh : copy all img file to /tftpboot/
- mkfirmware.sh : make firmware images in to tools/Image/
- mkupdate.sh : build update.img
- package.config : config how to pack your image
- Makefile : Eeasily command shortcut.

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build.sh Executable file
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#!/bin/bash
source ./package.config
FOLDER="`pwd`/${FOLDER_NAME}/"
echo "build dtb"
DTB_PATH=system-top.dtb
echo "dtc compile [${DTS_FOLDER}] to system-top.dtb"
cd ${DTS_FOLDER}
make ${DTB_TARGET} > /dev/null
E=$?
cd -
if [ "0${E}" -eq "0" ]; then
echo "dtb create ok"
else
echo "cmd [cd ${DTS_FOLDER} && make ${DTB_TARGET}] is error. try your self"
exit 1
fi
echo "copy kernel"
echo "cp ${FOLDER}/arch/arm64/boot/Image ./images/Image"
cp ${FOLDER}/arch/arm64/boot/Image ./images/Image
cd images/
echo "======make uimage=========================================="
mkimage -A arm64 -O linux -T kernel -C none -a ${KERNEL_ADDRESS} -e ${ENTRY_POINT} -n "${UIMAGE_DESC}" -d Image ${UIMAGE_NAME}
cd -
echo "done ./images/${UIMAGE_NAME}"
if [ "_$1" == "_1" ]; then
# if [ "_$2" == "_1" ]; then
echo "repack ramdisk"
TOP=`pwd`
cd images
T=`pwd`
echo "clean old, pwd:${T}"
fakeroot -- rm -fr rootfs_tmp/
echo "update modules"
mkdir -p rootfs_tmp/
fakeroot -- tar -xf ${RAM_ROOTFS} -C rootfs_tmp/
if [ -e "rootfs_tmp/rootfs_tmp" ]; then
fakeroot -- mv rootfs_tmp/rootfs_tmp/* rootfs_tmp/
fi
if [ -f "linux-5.15.0+-arm64.tar.gz" ]; then
fakeroot -- tar --keep-directory-symlink -xf "linux-5.15.0+-arm64.tar.gz" -C rootfs_tmp/
fi
fakeroot cp -r ramdisk_files/* rootfs_tmp/
cd rootfs_tmp/
echo "recreate ramdisk"
if [ ! -e "init" ]; then
echo -e "#!/bin/bash\\nexec /linuxrc" > init
chmod a+x init
fi
fakeroot -- bash -c "find ./* | cpio -H newc -o" | gzip -c > ../initrd.img
#sudo rm -fr rootfs_tmp/
cd ${TOP}
# fi
# echo "ramdisk boot ub"
# mkimage -f conf/fitImage-ramdisk.its -E -p 0x800 -B 0x200 ./images/boot-ramdisk.img
# echo "done ./images/boot-ramdisk.img"
else
echo "done"
fi

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build_kernel.sh Executable file
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#!/bin/bash
. package.config
CUR_DIR=`dirname $(realpath $0)`
CROSS_COMPILE=${CROSS_COMPILE:-aarch64-linux-gnu-}
if [ ! -e "${CROSS_COMPILE}gcc" ]; then
CROSS_COMPILE=aarch64-linux-gnu-
fi
FOLDER_NAME=${FOLDER_NAME:build}
FOLDER="`pwd`/${FOLDER_NAME}/"
KBUILD_BUILD_USER=acosail
KBUILD_BUILD_HOST=acosail
ARCH=arm64
export ARCH CROSS_COMPILE KBUILD_BUILD_USER KBUILD_BUILD_HOST
PARAMS="-C ${SRC} INSTALL_MOD_STRIP=1 O=${FOLDER} -j${CORES}"
echo "build kernel"
if [ ! -d "${FOLDER}" ]; then
mkdir ${FOLDER}
cp $CUR_DIR/conf/${CONFIG_NAME} ${FOLDER}.config
fi
CMD=
if [ "_$1" == "_deb" ]; then
echo "build debs"
CMD=bindeb-pkg
RET=$?
elif [ "_$1" == "_menu" ]; then
CMD=menuconfig
elif [ "_$1" == "_c" ]; then
CMD=
elif [ "_$1" == "_mrproper" ]; then
CMD=mrproper
else
CMD=targz-pkg
fi
make ${PARAMS} ${CMD}
RET=$?
if [ "$RET" -eq 0 ]; then
if [ "_${CMD}" == "_targz-pkg" ]; then
echo "copy kernel tar file to images/"
cp ${FOLDER}linux-5.15.0.bpo*.tar.gz $CUR_DIR/images/linux-5.15.0+-arm64.tar.gz
fi
cd $CUR_DIR
echo "current version:"
cat ${FOLDER}/include/config/kernel.release
echo "done"
else
echo "kernel build error!"
fi
exit $RET

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conf/std_config Normal file

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copy.sh Executable file
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#!/bin/bash
source ./package.config
echo "cp images/${UIMAGE_NAME} /tftpboot/"
cp images/${UIMAGE_NAME} /tftpboot/
echo "cp images/Image /tftpboot/"
cp images/Image /tftpboot/
#cp images/linux-*.gz /tftpboot/
if [ -e "images/initrd.img" ] ; then
echo "cp images/initrd.img /tftpboot/"
cp images/initrd.img /tftpboot/
fi
echo "cp images/system-top.dtb /tftpboot/${DTB_TARGET}"
cp images/system-top.dtb /tftpboot/${DTB_TARGET}

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# 1 "ft2004-devboard-xbhk-nas.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "ft2004-devboard-xbhk-nas.dts"
# 1 "ft2004-devboard-d4-dsk.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "ft2004-devboard-d4-dsk.dts"
/dts-v1/;
/memreserve/ 0x80000000 0x10000;
# 1 "ft2004-generic-psci-soc.dtsi" 1
# 1 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "../u-boot/include/dt-bindings/interrupt-controller/irq.h" 1
# 10 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 2
# 9 "ft2004-generic-psci-soc.dtsi" 2
/ {
compatible = "phytium,ft2004";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xc4000003>;
sys_poweroff = <0x84000008>;
sys_reset = <0x84000009>;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 1>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 1>;
};
};
gic: interrupt-controller@29900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x29900000 0 0x20000>,
<0x0 0x29980000 0 0x80000>,
<0x0 0x29c00000 0 0x10000>,
<0x0 0x29c10000 0 0x10000>,
<0x0 0x29c20000 0 0x10000>;
interrupts = <1 9 4>;
its: gic-its@29920000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x29920000 0x0 0x20000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 8>,
<1 14 8>,
<1 11 8>,
<1 10 8>;
clock-frequency = <48000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 8>;
};
clocks {
#address-cells = <2>;
#size-cells = <2>;
ranges;
clk250mhz: clk250mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
sysclk_48mhz: clk48mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
sysclk_600mhz: clk600mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
ranges;
gpio0: gpio@28004000 {
compatible = "phytium,gpio";
reg = <0x0 0x28004000 0x0 0x1000>;
interrupts = <0 10 4>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
porta {
compatible = "phytium,gpio-port";
reg = <0>;
nr-gpios = <8>;
};
portb {
compatible = "phytium,gpio-port";
reg = <1>;
nr-gpios = <8>;
};
};
gpio1: gpio@28005000 {
compatible = "phytium,gpio";
reg = <0x0 0x28005000 0x0 0x1000>;
interrupts = <0 11 4>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
porta {
compatible = "phytium,gpio-port";
reg = <0>;
nr-gpios = <8>;
};
portb {
compatible = "phytium,gpio-port";
reg = <1>;
nr-gpios = <8>;
};
};
uart0: uart@28000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28000000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 6 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@28001000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28001000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 7 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart2: uart@28002000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28002000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 8 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart3: uart@28003000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28003000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 9 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
sdci: sdci@28207c00 {
compatible = "phytium,sdci";
reg = <0x0 0x28207c00 0x0 0x100>;
interrupts = <0 20 4>,
<0 21 4>,
<0 22 4>;
clocks = <&sysclk_600mhz &sysclk_600mhz>;
clock-names = "phytium_sdc_clk";
no-sdio;
no-mmc;
no-dma-coherent;
};
watchdog0: watchdog@2800a000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2800b000 0x0 0x1000>,
<0x0 0x2800a000 0x0 0x1000>;
interrupts = <0 16 4>;
timeout-sec = <30>;
};
watchdog1: watchdog@28016000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x28017000 0x0 0x1000>,
<0x0 0x28016000 0x0 0x1000>;
interrupts = <0 17 4>;
timeout-sec = <30>;
};
rtc0: rtc@2800d000 {
compatible = "phytium,rtc";
reg = <0x0 0x2800d000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
clock-names = "rtc_pclk";
interrupts = <0 4 4>;
status = "disabled";
};
i2c0: i2c@28006000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28006000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c1: i2c@28007000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28007000 0x0 0x1000>;
interrupts = <0 13 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c2: i2c@28008000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28008000 0x0 0x1000>;
interrupts = <0 14 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c3: i2c@28009000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28009000 0x0 0x1000>;
interrupts = <0 15 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
spi0: spi@2800c000 {
compatible = "phytium,spi";
interrupts = <0 18 4>;
reg = <0x0 0x2800c000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
num-cs = <4>;
};
spi1: spi@28013000 {
compatible = "phytium,spi";
interrupts = <0 19 4>;
reg = <0x0 0x28013000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
num-cs = <4>;
};
qspi: qspi@28014000 {
compatible = "phytium,qspi";
reg = <0x0 0x28014000 0x0 0x1000>,
<0x0 0x0 0x0 0x02000000>;
reg-names = "qspi", "qspi_mm";
clocks = <&sysclk_600mhz>;
flash@0 {
spi-rx-bus-width = <1>;
spi-max-frequency = <600000000>;
};
};
pcie: pcie {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0x0 0x40000000 0x0 0x10000000>;
msi-parent = <&its>;
bus-range = <0x0 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0 28 4>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0 29 4>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0 30 4>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0 31 4>;
ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00f00000>,
<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
<0x03000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
};
phytium_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0>;
snps,rd_osr_lmt = <0>;
snps,blen = <0 0 0 0 16 8 4>;
};
gmac0: eth@2820c000 {
compatible = "snps,dwmac";
reg = <0x0 0x2820c000 0x0 0x2000>;
interrupts = <0 49 4>;
interrupt-names = "macirq";
clocks = <&clk250mhz>;
clock-names = "stmmaceth";
status = "disabled";
snps,pbl = <16>;
snps,fixed-burst;
snps,axi-config = <&phytium_axi_setup>;
snps,force_sf_dma_mode;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
max-frame-size = <9000>;
};
gmac1: eth@28210000 {
compatible = "snps,dwmac";
reg = <0x0 0x28210000 0x0 0x2000>;
interrupts = <0 50 4>;
interrupt-names = "macirq";
clocks = <&clk250mhz>;
clock-names = "stmmaceth";
status = "disabled";
snps,pbl = <16>;
snps,fixed-burst;
snps,axi-config = <&phytium_axi_setup>;
snps,force_sf_dma_mode;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
snps,rx-queues-to-use = <2>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
max-frame-size = <9000>;
};
can0: can@28207000 {
compatible = "phytium,can";
reg = <0x0 0x28207000 0x0 0x400>;
interrupts = <0 87 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@28207400 {
compatible = "phytium,can";
reg = <0x0 0x28207400 0x0 0x400>;
interrupts = <0 91 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can2: can@028207800 {
compatible = "phytium,can";
reg = <0x0 0x28207800 0x0 0x400>;
interrupts = <0 92 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
hda: hda@28206000 {
compatible = "phytium,hda";
reg = <0 0x28206000 0x0 0x1000>;
interrupts = <0 23 4>;
clocks = <&sysclk_48mhz>;
clock-names = "phytium_hda_clk";
};
mbox: mailbox@2a000000 {
compatible = "phytium,mbox";
reg = <0x0 0x2a000000 0x0 0x1000>;
interrupts = <0 48 4>;
#mbox-cells = <1>;
clocks = <&sysclk_48mhz>;
clock-names = "apb_pclk";
};
sram: sram@2a006000 {
compatible = "phytium,ft2004-sram-ns","mmio-sram";
reg = <0x0 0x2a006000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x2a006000 0x2000>;
scpi_lpri: scpi-shmem@0 {
compatible = "phytium,ft2004-scpi-shmem";
reg = <0x1000 0x800>;
};
};
scpi_protocol: scpi {
compatible = "arm,scpi";
mboxes = <&mbox 0>;
shmem = <&scpi_lpri>;
clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>;
clock-output-names = "c0", "c1";
};
};
scpi_sensors: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
};
};
# 12 "ft2004-devboard-d4-dsk.dts" 2
/{
model = "FT-2000/4-D4-DSK Development Board";
compatible = "phytium,ft-2004";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "uart1:115200n8";
};
memory@00{
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
};
memory@01{
device_type = "memory";
reg = <0x20 0x00000000 0x1 0x00000000>;
};
firmware {
};
};
&rtc0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&gmac0 {
status = "ok";
phy-mode = "rgmii-rxid";
};
&gmac1 {
status = "disabled";
phy-mode = "rgmii-rxid";
};
&spi0 {
status = "ok";
};
&qspi {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};

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dts_files=$(wildcard *.dts)
objects=$(patsubst %.dts,%.dtb,$(dts_files))
desc:
@echo "You can build dtbs as below:"
@echo $(objects)
$(objects):
cpp -nostdinc -I. -I../../../tmp_kernel_5.15/include/ -undef -x assembler-with-cpp $(patsubst %.dtb,%.dts,$@) > 0system-top.dts
dtc -O dtb -I dts -o ../../system-top.dtb 0system-top.dts

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# 1 "ft2004-devboard-d4-dsk.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "ft2004-devboard-d4-dsk.dts"
/dts-v1/;
/memreserve/ 0x80000000 0x10000;
# 1 "ft2004-generic-psci-soc.dtsi" 1
# 1 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "../u-boot/include/dt-bindings/interrupt-controller/irq.h" 1
# 10 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 2
# 9 "ft2004-generic-psci-soc.dtsi" 2
/ {
compatible = "phytium,ft2004";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xc4000003>;
sys_poweroff = <0x84000008>;
sys_reset = <0x84000009>;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 1>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 1>;
};
};
gic: interrupt-controller@29900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x29900000 0 0x20000>,
<0x0 0x29980000 0 0x80000>,
<0x0 0x29c00000 0 0x10000>,
<0x0 0x29c10000 0 0x10000>,
<0x0 0x29c20000 0 0x10000>;
interrupts = <1 9 4>;
its: gic-its@29920000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x29920000 0x0 0x20000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 8>,
<1 14 8>,
<1 11 8>,
<1 10 8>;
clock-frequency = <48000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 8>;
};
clocks {
#address-cells = <2>;
#size-cells = <2>;
ranges;
clk250mhz: clk250mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
sysclk_48mhz: clk48mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
sysclk_600mhz: clk600mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
ranges;
gpio0: gpio@28004000 {
compatible = "phytium,gpio";
reg = <0x0 0x28004000 0x0 0x1000>;
interrupts = <0 10 4>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
porta {
compatible = "phytium,gpio-port";
reg = <0>;
nr-gpios = <8>;
};
portb {
compatible = "phytium,gpio-port";
reg = <1>;
nr-gpios = <8>;
};
};
gpio1: gpio@28005000 {
compatible = "phytium,gpio";
reg = <0x0 0x28005000 0x0 0x1000>;
interrupts = <0 11 4>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
porta {
compatible = "phytium,gpio-port";
reg = <0>;
nr-gpios = <8>;
};
portb {
compatible = "phytium,gpio-port";
reg = <1>;
nr-gpios = <8>;
};
};
uart0: uart@28000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28000000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 6 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@28001000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28001000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 7 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart2: uart@28002000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28002000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 8 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart3: uart@28003000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28003000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 9 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
sdci: sdci@28207c00 {
compatible = "phytium,sdci";
reg = <0x0 0x28207c00 0x0 0x100>;
interrupts = <0 20 4>,
<0 21 4>,
<0 22 4>;
clocks = <&sysclk_600mhz &sysclk_600mhz>;
clock-names = "phytium_sdc_clk";
no-sdio;
no-mmc;
no-dma-coherent;
};
watchdog0: watchdog@2800a000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2800b000 0x0 0x1000>,
<0x0 0x2800a000 0x0 0x1000>;
interrupts = <0 16 4>;
timeout-sec = <30>;
};
watchdog1: watchdog@28016000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x28017000 0x0 0x1000>,
<0x0 0x28016000 0x0 0x1000>;
interrupts = <0 17 4>;
timeout-sec = <30>;
};
rtc0: rtc@2800d000 {
compatible = "phytium,rtc";
reg = <0x0 0x2800d000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
clock-names = "rtc_pclk";
interrupts = <0 4 4>;
status = "disabled";
};
i2c0: i2c@28006000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28006000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c1: i2c@28007000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28007000 0x0 0x1000>;
interrupts = <0 13 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c2: i2c@28008000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28008000 0x0 0x1000>;
interrupts = <0 14 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c3: i2c@28009000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28009000 0x0 0x1000>;
interrupts = <0 15 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
spi0: spi@2800c000 {
compatible = "phytium,spi";
interrupts = <0 18 4>;
reg = <0x0 0x2800c000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
num-cs = <4>;
};
spi1: spi@28013000 {
compatible = "phytium,spi";
interrupts = <0 19 4>;
reg = <0x0 0x28013000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
num-cs = <4>;
};
qspi: qspi@28014000 {
compatible = "phytium,qspi";
reg = <0x0 0x28014000 0x0 0x1000>,
<0x0 0x0 0x0 0x02000000>;
reg-names = "qspi", "qspi_mm";
clocks = <&sysclk_600mhz>;
flash@0 {
spi-rx-bus-width = <1>;
spi-max-frequency = <600000000>;
};
};
pcie: pcie {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0x0 0x40000000 0x0 0x10000000>;
msi-parent = <&its>;
bus-range = <0x0 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0 28 4>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0 29 4>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0 30 4>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0 31 4>;
ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00f00000>,
<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
<0x03000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
};
phytium_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0>;
snps,rd_osr_lmt = <0>;
snps,blen = <0 0 0 0 16 8 4>;
};
gmac0: eth@2820c000 {
compatible = "snps,dwmac";
reg = <0x0 0x2820c000 0x0 0x2000>;
interrupts = <0 49 4>;
interrupt-names = "macirq";
clocks = <&clk250mhz>;
clock-names = "stmmaceth";
status = "disabled";
snps,pbl = <16>;
snps,fixed-burst;
snps,axi-config = <&phytium_axi_setup>;
snps,force_sf_dma_mode;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
max-frame-size = <9000>;
};
gmac1: eth@28210000 {
compatible = "snps,dwmac";
reg = <0x0 0x28210000 0x0 0x2000>;
interrupts = <0 50 4>;
interrupt-names = "macirq";
clocks = <&clk250mhz>;
clock-names = "stmmaceth";
status = "disabled";
snps,pbl = <16>;
snps,fixed-burst;
snps,axi-config = <&phytium_axi_setup>;
snps,force_sf_dma_mode;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
snps,rx-queues-to-use = <2>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
max-frame-size = <9000>;
};
can0: can@28207000 {
compatible = "phytium,can";
reg = <0x0 0x28207000 0x0 0x400>;
interrupts = <0 87 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@28207400 {
compatible = "phytium,can";
reg = <0x0 0x28207400 0x0 0x400>;
interrupts = <0 91 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can2: can@028207800 {
compatible = "phytium,can";
reg = <0x0 0x28207800 0x0 0x400>;
interrupts = <0 92 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
hda: hda@28206000 {
compatible = "phytium,hda";
reg = <0 0x28206000 0x0 0x1000>;
interrupts = <0 23 4>;
clocks = <&sysclk_48mhz>;
clock-names = "phytium_hda_clk";
};
mbox: mailbox@2a000000 {
compatible = "phytium,mbox";
reg = <0x0 0x2a000000 0x0 0x1000>;
interrupts = <0 48 4>;
#mbox-cells = <1>;
clocks = <&sysclk_48mhz>;
clock-names = "apb_pclk";
};
sram: sram@2a006000 {
compatible = "phytium,ft2004-sram-ns","mmio-sram";
reg = <0x0 0x2a006000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x2a006000 0x2000>;
scpi_lpri: scpi-shmem@0 {
compatible = "phytium,ft2004-scpi-shmem";
reg = <0x1000 0x800>;
};
};
scpi_protocol: scpi {
compatible = "arm,scpi";
mboxes = <&mbox 0>;
shmem = <&scpi_lpri>;
clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>;
clock-output-names = "c0", "c1";
};
};
scpi_sensors: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
};
};
# 12 "ft2004-devboard-d4-dsk.dts" 2
/{
model = "FT-2000/4-D4-DSK Development Board";
compatible = "phytium,ft-2004";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "uart1:115200n8";
};
memory@00{
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
};
memory@01{
device_type = "memory";
reg = <0x20 0x00000000 0x1 0x00000000>;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&rtc0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&gmac0 {
status = "ok";
phy-mode = "rgmii-rxid";
};
&gmac1 {
status = "disabled";
phy-mode = "rgmii-rxid";
};
&spi0 {
status = "ok";
};
&qspi {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};

View File

@ -0,0 +1,556 @@
# 1 "ft2004-devboard-d4-dsk.dts"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "ft2004-devboard-d4-dsk.dts"
/dts-v1/;
/memreserve/ 0x80000000 0x10000;
# 1 "ft2004-generic-psci-soc.dtsi" 1
# 1 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 1
# 9 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h"
# 1 "../u-boot/include/dt-bindings/interrupt-controller/irq.h" 1
# 10 "../u-boot/include/dt-bindings/interrupt-controller/arm-gic.h" 2
# 9 "ft2004-generic-psci-soc.dtsi" 2
/ {
compatible = "phytium,ft2004";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac1;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
cpu_suspend = <0xc4000001>;
cpu_off = <0x84000002>;
cpu_on = <0xc4000003>;
sys_poweroff = <0x84000008>;
sys_reset = <0x84000009>;
};
cpus {
#address-cells = <0x2>;
#size-cells = <0x0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 0>;
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 1>;
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
numa-node-id = <0>;
clocks = <&scpi_dvfs 1>;
};
};
gic: interrupt-controller@29900000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
reg = <0x0 0x29900000 0 0x20000>,
<0x0 0x29980000 0 0x80000>,
<0x0 0x29c00000 0 0x10000>,
<0x0 0x29c10000 0 0x10000>,
<0x0 0x29c20000 0 0x10000>;
interrupts = <1 9 4>;
its: gic-its@29920000 {
compatible = "arm,gic-v3-its";
msi-controller;
reg = <0x0 0x29920000 0x0 0x20000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 8>,
<1 14 8>,
<1 11 8>,
<1 10 8>;
clock-frequency = <48000000>;
};
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <1 7 8>;
};
clocks {
#address-cells = <2>;
#size-cells = <2>;
ranges;
clk250mhz: clk250mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <250000000>;
};
sysclk_48mhz: clk48mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
sysclk_600mhz: clk600mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <600000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
dma-coherent;
ranges;
gpio0: gpio@28004000 {
compatible = "phytium,gpio";
reg = <0x0 0x28004000 0x0 0x1000>;
interrupts = <0 10 4>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
porta {
compatible = "phytium,gpio-port";
reg = <0>;
nr-gpios = <8>;
};
portb {
compatible = "phytium,gpio-port";
reg = <1>;
nr-gpios = <8>;
};
};
gpio1: gpio@28005000 {
compatible = "phytium,gpio";
reg = <0x0 0x28005000 0x0 0x1000>;
interrupts = <0 11 4>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <1>;
#size-cells = <0>;
porta {
compatible = "phytium,gpio-port";
reg = <0>;
nr-gpios = <8>;
};
portb {
compatible = "phytium,gpio-port";
reg = <1>;
nr-gpios = <8>;
};
};
uart0: uart@28000000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28000000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 6 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart1: uart@28001000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28001000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 7 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart2: uart@28002000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28002000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 8 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
uart3: uart@28003000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x28003000 0x0 0x1000>;
baud = <115200>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <0 9 4>;
clocks = <&sysclk_48mhz &sysclk_48mhz>;
clock-names = "uartclk", "apb_pclk";
};
sdci: sdci@28207c00 {
compatible = "phytium,sdci";
reg = <0x0 0x28207c00 0x0 0x100>;
interrupts = <0 20 4>,
<0 21 4>,
<0 22 4>;
clocks = <&sysclk_600mhz &sysclk_600mhz>;
clock-names = "phytium_sdc_clk";
no-sdio;
no-mmc;
no-dma-coherent;
};
watchdog0: watchdog@2800a000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x2800b000 0x0 0x1000>,
<0x0 0x2800a000 0x0 0x1000>;
interrupts = <0 16 4>;
timeout-sec = <30>;
};
watchdog1: watchdog@28016000 {
compatible = "arm,sbsa-gwdt";
reg = <0x0 0x28017000 0x0 0x1000>,
<0x0 0x28016000 0x0 0x1000>;
interrupts = <0 17 4>;
timeout-sec = <30>;
};
rtc0: rtc@2800d000 {
compatible = "phytium,rtc";
reg = <0x0 0x2800d000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
clock-names = "rtc_pclk";
interrupts = <0 4 4>;
status = "disabled";
};
i2c0: i2c@28006000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28006000 0x0 0x1000>;
interrupts = <0 12 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c1: i2c@28007000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28007000 0x0 0x1000>;
interrupts = <0 13 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c2: i2c@28008000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28008000 0x0 0x1000>;
interrupts = <0 14 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
i2c3: i2c@28009000 {
compatible = "snps,designware-i2c";
reg = <0x0 0x28009000 0x0 0x1000>;
interrupts = <0 15 4>;
clocks = <&sysclk_48mhz>;
status = "disabled";
};
spi0: spi@2800c000 {
compatible = "phytium,spi";
interrupts = <0 18 4>;
reg = <0x0 0x2800c000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
num-cs = <4>;
};
spi1: spi@28013000 {
compatible = "phytium,spi";
interrupts = <0 19 4>;
reg = <0x0 0x28013000 0x0 0x1000>;
clocks = <&sysclk_48mhz>;
num-cs = <4>;
};
qspi: qspi@28014000 {
compatible = "phytium,qspi";
reg = <0x0 0x28014000 0x0 0x1000>,
<0x0 0x0 0x0 0x02000000>;
reg-names = "qspi", "qspi_mm";
clocks = <&sysclk_600mhz>;
flash@0 {
spi-rx-bus-width = <1>;
spi-max-frequency = <600000000>;
};
};
pcie: pcie {
compatible = "pci-host-ecam-generic";
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
reg = <0x0 0x40000000 0x0 0x10000000>;
msi-parent = <&its>;
bus-range = <0x0 0xff>;
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0 28 4>,
<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0 29 4>,
<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0 30 4>,
<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0 31 4>;
ranges = <0x01000000 0x00 0x00000000 0x0 0x50000000 0x0 0x00f00000>,
<0x02000000 0x00 0x58000000 0x0 0x58000000 0x0 0x28000000>,
<0x03000000 0x10 0x00000000 0x10 0x00000000 0x10 0x00000000>;
};
phytium_axi_setup: stmmac-axi-config {
snps,wr_osr_lmt = <0>;
snps,rd_osr_lmt = <0>;
snps,blen = <0 0 0 0 16 8 4>;
};
gmac0: eth@2820c000 {
compatible = "snps,dwmac";
reg = <0x0 0x2820c000 0x0 0x2000>;
interrupts = <0 49 4>;
interrupt-names = "macirq";
clocks = <&clk250mhz>;
clock-names = "stmmaceth";
status = "disabled";
snps,pbl = <16>;
snps,fixed-burst;
snps,axi-config = <&phytium_axi_setup>;
snps,force_sf_dma_mode;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
max-frame-size = <9000>;
};
gmac1: eth@28210000 {
compatible = "snps,dwmac";
reg = <0x0 0x28210000 0x0 0x2000>;
interrupts = <0 50 4>;
interrupt-names = "macirq";
clocks = <&clk250mhz>;
clock-names = "stmmaceth";
status = "disabled";
snps,pbl = <16>;
snps,fixed-burst;
snps,axi-config = <&phytium_axi_setup>;
snps,force_sf_dma_mode;
snps,multicast-filter-bins = <64>;
snps,perfect-filter-entries = <128>;
snps,rx-queues-to-use = <2>;
tx-fifo-depth = <4096>;
rx-fifo-depth = <4096>;
max-frame-size = <9000>;
};
can0: can@28207000 {
compatible = "phytium,can";
reg = <0x0 0x28207000 0x0 0x400>;
interrupts = <0 87 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@28207400 {
compatible = "phytium,can";
reg = <0x0 0x28207400 0x0 0x400>;
interrupts = <0 91 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can2: can@028207800 {
compatible = "phytium,can";
reg = <0x0 0x28207800 0x0 0x400>;
interrupts = <0 92 4>;
clocks = <&sysclk_600mhz>;
clock-names = "phytium_can_clk";
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
hda: hda@28206000 {
compatible = "phytium,hda";
reg = <0 0x28206000 0x0 0x1000>;
interrupts = <0 23 4>;
clocks = <&sysclk_48mhz>;
clock-names = "phytium_hda_clk";
};
mbox: mailbox@2a000000 {
compatible = "phytium,mbox";
reg = <0x0 0x2a000000 0x0 0x1000>;
interrupts = <0 48 4>;
#mbox-cells = <1>;
clocks = <&sysclk_48mhz>;
clock-names = "apb_pclk";
};
sram: sram@2a006000 {
compatible = "phytium,ft2004-sram-ns","mmio-sram";
reg = <0x0 0x2a006000 0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x2a006000 0x2000>;
scpi_lpri: scpi-shmem@0 {
compatible = "phytium,ft2004-scpi-shmem";
reg = <0x1000 0x800>;
};
};
scpi_protocol: scpi {
compatible = "arm,scpi";
mboxes = <&mbox 0>;
shmem = <&scpi_lpri>;
clocks {
compatible = "arm,scpi-clocks";
scpi_dvfs: scpi_clocks@0 {
compatible = "arm,scpi-dvfs-clocks";
#clock-cells = <1>;
clock-indices = <0>, <1>;
clock-output-names = "c0", "c1";
};
};
scpi_sensors: sensors {
compatible = "arm,scpi-sensors";
#thermal-sensor-cells = <1>;
};
};
};
};
# 12 "ft2004-devboard-d4-dsk.dts" 2
/{
model = "FT-2000/4-D4-DSK Development Board";
compatible = "phytium,ft-2004";
#address-cells = <2>;
#size-cells = <2>;
chosen {
stdout-path = "uart1:115200n8";
};
memory@00{
device_type = "memory";
reg = <0x0 0x80000000 0x1 0x00000000>;
};
memory@01{
device_type = "memory";
reg = <0x20 0x00000000 0x1 0x00000000>;
};
firmware {
// optee {
// compatible = "linaro,optee-tz";
// method = "smc";
// };
};
};
&rtc0 {
status = "ok";
};
&uart1 {
status = "ok";
};
&gmac0 {
status = "ok";
phy-mode = "rgmii-rxid";
};
&gmac1 {
status = "disabled";
phy-mode = "rgmii-rxid";
};
&spi0 {
status = "ok";
};
&qspi {
status = "ok";
};
&i2c0 {
status = "ok";
};
&i2c1 {
status = "ok";
};

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# <file system> <mount pt> <type> <options> <dump> <pass>
/dev/root / ext2 rw,noauto 0 1
proc /proc proc defaults 0 0
devtmpfs /dev devtmpfs defaults 0 0
devpts /dev/pts devpts defaults,gid=5,mode=620,ptmxmode=0666 0 0
tmpfs /dev/shm tmpfs mode=1777 0 0
tmpfs /tmp tmpfs mode=1777 0 0
tmpfs /run tmpfs mode=0755,nosuid,nodev 0 0
sysfs /sys sysfs defaults 0 0

326
images/ramdisk_files/init2 Executable file
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#!/bin/sh
# Default PATH differs between shells, and is not automatically exported
# by klibc dash. Make it consistent.
export PATH=/sbin:/usr/sbin:/bin:/usr/bin
[ -d /dev ] || mkdir -m 0755 /dev
[ -d /root ] || mkdir -m 0700 /root
[ -d /sys ] || mkdir /sys
[ -d /proc ] || mkdir /proc
[ -d /tmp ] || mkdir /tmp
mkdir -p /var/lock
mount -t sysfs -o nodev,noexec,nosuid sysfs /sys
mount -t proc -o nodev,noexec,nosuid proc /proc
# shellcheck disable=SC2013
for x in $(cat /proc/cmdline); do
case $x in
initramfs.clear)
clear
;;
quiet)
quiet=y
;;
esac
done
if [ "$quiet" != "y" ]; then
quiet=n
echo "Loading, please wait..."
fi
export quiet
# Note that this only becomes /dev on the real filesystem if udev's scripts
# are used; which they will be, but it's worth pointing out
mount -t devtmpfs -o nosuid,mode=0755 udev /dev
mkdir /dev/pts
mount -t devpts -o noexec,nosuid,gid=5,mode=0620 devpts /dev/pts || true
# Export the dpkg architecture
export DPKG_ARCH=
. /conf/arch.conf
# Set modprobe env
export MODPROBE_OPTIONS="-qb"
# Export relevant variables
export ROOT=
export ROOTDELAY=
export ROOTFLAGS=
export ROOTFSTYPE=
export IP=
export DEVICE=
export BOOT=
export BOOTIF=
export UBIMTD=
export break=
export init=/sbin/init
export readonly=y
export rootmnt=/root
export debug=
export panic=
export blacklist=
export resume=
export resume_offset=
export noresume=
export drop_caps=
export fastboot=n
export forcefsck=n
export fsckfix=
# Bring in the main config
. /conf/initramfs.conf
for conf in conf/conf.d/*; do
[ -f "${conf}" ] && . "${conf}"
done
. /scripts/functions
# Parse command line options
# shellcheck disable=SC2013
for x in $(cat /proc/cmdline); do
case $x in
init=*)
init=${x#init=}
;;
root=*)
ROOT=${x#root=}
if [ -z "${BOOT}" ] && [ "$ROOT" = "/dev/nfs" ]; then
BOOT=nfs
fi
;;
rootflags=*)
ROOTFLAGS="-o ${x#rootflags=}"
;;
rootfstype=*)
ROOTFSTYPE="${x#rootfstype=}"
;;
rootdelay=*)
ROOTDELAY="${x#rootdelay=}"
case ${ROOTDELAY} in
*[![:digit:].]*)
ROOTDELAY=
;;
esac
;;
nfsroot=*)
# shellcheck disable=SC2034
NFSROOT="${x#nfsroot=}"
;;
initramfs.runsize=*)
RUNSIZE="${x#initramfs.runsize=}"
;;
ip=*)
IP="${x#ip=}"
;;
boot=*)
BOOT=${x#boot=}
;;
ubi.mtd=*)
UBIMTD=${x#ubi.mtd=}
;;
resume=*)
RESUME="${x#resume=}"
;;
resume_offset=*)
resume_offset="${x#resume_offset=}"
;;
noresume)
noresume=y
;;
drop_capabilities=*)
drop_caps="-d ${x#drop_capabilities=}"
;;
panic=*)
panic="${x#panic=}"
;;
ro)
readonly=y
;;
rw)
readonly=n
;;
debug)
debug=y
quiet=n
if [ -n "${netconsole}" ]; then
log_output=/dev/kmsg
else
log_output=/run/initramfs/initramfs.debug
fi
set -x
;;
debug=*)
debug=y
quiet=n
set -x
;;
break=*)
break=${x#break=}
;;
break)
break=premount
;;
blacklist=*)
blacklist=${x#blacklist=}
;;
netconsole=*)
netconsole=${x#netconsole=}
[ "x$debug" = "xy" ] && log_output=/dev/kmsg
;;
BOOTIF=*)
BOOTIF=${x#BOOTIF=}
;;
fastboot|fsck.mode=skip)
fastboot=y
;;
forcefsck|fsck.mode=force)
forcefsck=y
;;
fsckfix|fsck.repair=yes)
fsckfix=y
;;
fsck.repair=no)
fsckfix=n
;;
esac
done
# Default to BOOT=local if no boot script defined.
if [ -z "${BOOT}" ]; then
BOOT=local
fi
if [ -n "${noresume}" ] || [ "$RESUME" = none ]; then
noresume=y
else
resume=${RESUME:-}
fi
mount -t tmpfs -o "nodev,noexec,nosuid,size=${RUNSIZE:-10%},mode=0755" tmpfs /run
mkdir -m 0700 /run/initramfs
if [ -n "$log_output" ]; then
exec >$log_output 2>&1
unset log_output
fi
maybe_break top
# Don't do log messages here to avoid confusing graphical boots
run_scripts /scripts/init-top
maybe_break modules
[ "$quiet" != "y" ] && log_begin_msg "Loading essential drivers"
[ -n "${netconsole}" ] && modprobe netconsole netconsole="${netconsole}"
load_modules
[ "$quiet" != "y" ] && log_end_msg
starttime="$(_uptime)"
starttime=$((starttime + 1)) # round up
export starttime
if [ "$ROOTDELAY" ]; then
sleep "$ROOTDELAY"
fi
maybe_break premount
[ "$quiet" != "y" ] && log_begin_msg "Running /scripts/init-premount"
run_scripts /scripts/init-premount
[ "$quiet" != "y" ] && log_end_msg
maybe_break mount
log_begin_msg "Mounting root file system"
# Always load local and nfs (since these might be needed for /etc or
# /usr, irrespective of the boot script used to mount the rootfs).
. /scripts/local
. /scripts/nfs
. /scripts/${BOOT}
parse_numeric "${ROOT}"
maybe_break mountroot
mount_top
mount_premount
mountroot
log_end_msg
if read_fstab_entry /usr; then
log_begin_msg "Mounting /usr file system"
mountfs /usr
log_end_msg
fi
# Mount cleanup
mount_bottom
nfs_bottom
local_bottom
maybe_break bottom
[ "$quiet" != "y" ] && log_begin_msg "Running /scripts/init-bottom"
# We expect udev's init-bottom script to move /dev to ${rootmnt}/dev
run_scripts /scripts/init-bottom
[ "$quiet" != "y" ] && log_end_msg
# Move /run to the root
mount -n -o move /run ${rootmnt}/run
validate_init() {
run-init -n "${rootmnt}" "${1}"
}
# Check init is really there
if ! validate_init "$init"; then
echo "Target filesystem doesn't have requested ${init}."
init=
for inittest in /sbin/init /etc/init /bin/init /bin/sh; do
if validate_init "${inittest}"; then
init="$inittest"
break
fi
done
fi
# No init on rootmount
if ! validate_init "${init}" ; then
panic "No init found. Try passing init= bootarg."
fi
maybe_break init
# don't leak too much of env - some init(8) don't clear it
# (keep init, rootmnt, drop_caps)
unset debug
unset MODPROBE_OPTIONS
unset DPKG_ARCH
unset ROOTFLAGS
unset ROOTFSTYPE
unset ROOTDELAY
unset ROOT
unset IP
unset BOOT
unset BOOTIF
unset DEVICE
unset UBIMTD
unset blacklist
unset break
unset noresume
unset panic
unset quiet
unset readonly
unset resume
unset resume_offset
unset noresume
unset fastboot
unset forcefsck
unset fsckfix
unset starttime
# Move virtual filesystems over to the real filesystem
mount -n -o move /sys ${rootmnt}/sys
mount -n -o move /proc ${rootmnt}/proc
# Chain to real filesystem
# shellcheck disable=SC2086,SC2094
exec run-init ${drop_caps} "${rootmnt}" "${init}" "$@" <"${rootmnt}/dev/console" >"${rootmnt}/dev/console" 2>&1
echo "Something went badly wrong in the initramfs."
panic "Please file a bug on initramfs-tools."

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package.config Normal file
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CROSS_COMPILE=/opt/gcc-arm-10.2-2020.11-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-
FOLDER_NAME=build_none
CONFIG_NAME=std_config
CORES=8
SRC=../tmp_kernel_5.15/
RAM_ROOTFS=rootfs.tar.gz
# RAM_ROOTFS=rootfs_tmp.tgz
# ft2004 xibeihangkonggongye
DTS_FOLDER=images/dts/ft2004/
DTB_TARGET=ft2004-devboard-xbhk-nas.dtb
KERNEL_ADDRESS=0x90200000
ENTRY_POINT=0x90200000
UIMAGE_NAME=uImage_bpo7_FT2004
UIMAGE_DESC="FT2004 Kernel"