511 lines
11 KiB
C
511 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Thunderbolt link controller support
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*
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* Copyright (C) 2019, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#include "tb.h"
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/**
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* tb_lc_read_uuid() - Read switch UUID from link controller common register
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* @sw: Switch whose UUID is read
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* @uuid: UUID is placed here
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*/
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int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid)
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{
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if (!sw->cap_lc)
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return -EINVAL;
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return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);
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}
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static int read_lc_desc(struct tb_switch *sw, u32 *desc)
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{
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if (!sw->cap_lc)
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return -EINVAL;
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return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);
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}
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static int find_port_lc_cap(struct tb_port *port)
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{
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struct tb_switch *sw = port->sw;
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int start, phys, ret, size;
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u32 desc;
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ret = read_lc_desc(sw, &desc);
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if (ret)
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return ret;
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/* Start of port LC registers */
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start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
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size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
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phys = tb_phy_port_from_link(port->port);
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return sw->cap_lc + start + phys * size;
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}
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static int tb_lc_set_port_configured(struct tb_port *port, bool configured)
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{
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bool upstream = tb_is_upstream_port(port);
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struct tb_switch *sw = port->sw;
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u32 ctrl, lane;
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int cap, ret;
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if (sw->generation < 2)
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return 0;
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cap = find_port_lc_cap(port);
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if (cap < 0)
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return cap;
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ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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/* Resolve correct lane */
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if (port->port % 2)
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lane = TB_LC_SX_CTRL_L1C;
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else
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lane = TB_LC_SX_CTRL_L2C;
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if (configured) {
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ctrl |= lane;
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if (upstream)
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ctrl |= TB_LC_SX_CTRL_UPSTREAM;
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} else {
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ctrl &= ~lane;
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if (upstream)
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ctrl &= ~TB_LC_SX_CTRL_UPSTREAM;
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}
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return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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}
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/**
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* tb_lc_configure_port() - Let LC know about configured port
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* @port: Port that is set as configured
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*
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* Sets the port configured for power management purposes.
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*/
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int tb_lc_configure_port(struct tb_port *port)
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{
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return tb_lc_set_port_configured(port, true);
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}
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/**
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* tb_lc_unconfigure_port() - Let LC know about unconfigured port
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* @port: Port that is set as configured
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*
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* Sets the port unconfigured for power management purposes.
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*/
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void tb_lc_unconfigure_port(struct tb_port *port)
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{
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tb_lc_set_port_configured(port, false);
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}
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static int tb_lc_set_xdomain_configured(struct tb_port *port, bool configure)
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{
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struct tb_switch *sw = port->sw;
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u32 ctrl, lane;
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int cap, ret;
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if (sw->generation < 2)
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return 0;
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cap = find_port_lc_cap(port);
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if (cap < 0)
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return cap;
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ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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/* Resolve correct lane */
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if (port->port % 2)
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lane = TB_LC_SX_CTRL_L1D;
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else
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lane = TB_LC_SX_CTRL_L2D;
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if (configure)
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ctrl |= lane;
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else
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ctrl &= ~lane;
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return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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}
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/**
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* tb_lc_configure_xdomain() - Inform LC that the link is XDomain
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* @port: Switch downstream port connected to another host
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*
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* Sets the lane configured for XDomain accordingly so that the LC knows
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* about this. Returns %0 in success and negative errno in failure.
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*/
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int tb_lc_configure_xdomain(struct tb_port *port)
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{
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return tb_lc_set_xdomain_configured(port, true);
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}
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/**
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* tb_lc_unconfigure_xdomain() - Unconfigure XDomain from port
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* @port: Switch downstream port that was connected to another host
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*
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* Unsets the lane XDomain configuration.
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*/
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void tb_lc_unconfigure_xdomain(struct tb_port *port)
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{
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tb_lc_set_xdomain_configured(port, false);
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}
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/**
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* tb_lc_start_lane_initialization() - Start lane initialization
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* @port: Device router lane 0 adapter
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*
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* Starts lane initialization for @port after the router resumed from
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* sleep. Should be called for those downstream lane adapters that were
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* not connected (tb_lc_configure_port() was not called) before sleep.
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*
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* Returns %0 in success and negative errno in case of failure.
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*/
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int tb_lc_start_lane_initialization(struct tb_port *port)
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{
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struct tb_switch *sw = port->sw;
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int ret, cap;
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u32 ctrl;
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if (!tb_route(sw))
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return 0;
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if (sw->generation < 2)
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return 0;
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cap = find_port_lc_cap(port);
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if (cap < 0)
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return cap;
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ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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ctrl |= TB_LC_SX_CTRL_SLI;
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return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
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}
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static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset,
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unsigned int flags)
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{
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u32 ctrl;
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int ret;
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/*
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* Enable wake on PCIe and USB4 (wake coming from another
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* router).
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*/
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ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
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offset + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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ctrl &= ~(TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD | TB_LC_SX_CTRL_WODPC |
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TB_LC_SX_CTRL_WODPD | TB_LC_SX_CTRL_WOP | TB_LC_SX_CTRL_WOU4);
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if (flags & TB_WAKE_ON_CONNECT)
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ctrl |= TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD;
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if (flags & TB_WAKE_ON_USB4)
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ctrl |= TB_LC_SX_CTRL_WOU4;
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if (flags & TB_WAKE_ON_PCIE)
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ctrl |= TB_LC_SX_CTRL_WOP;
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if (flags & TB_WAKE_ON_DP)
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ctrl |= TB_LC_SX_CTRL_WODPC | TB_LC_SX_CTRL_WODPD;
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return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);
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}
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/**
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* tb_lc_set_wake() - Enable/disable wake
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* @sw: Switch whose wakes to configure
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* @flags: Wakeup flags (%0 to disable)
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*
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* For each LC sets wake bits accordingly.
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*/
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int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags)
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{
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int start, size, nlc, ret, i;
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u32 desc;
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if (sw->generation < 2)
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return 0;
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if (!tb_route(sw))
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return 0;
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ret = read_lc_desc(sw, &desc);
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if (ret)
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return ret;
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/* Figure out number of link controllers */
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nlc = desc & TB_LC_DESC_NLC_MASK;
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start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
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size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
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/* For each link controller set sleep bit */
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for (i = 0; i < nlc; i++) {
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unsigned int offset = sw->cap_lc + start + i * size;
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ret = tb_lc_set_wake_one(sw, offset, flags);
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if (ret)
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return ret;
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}
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return 0;
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}
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/**
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* tb_lc_set_sleep() - Inform LC that the switch is going to sleep
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* @sw: Switch to set sleep
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*
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* Let the switch link controllers know that the switch is going to
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* sleep.
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*/
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int tb_lc_set_sleep(struct tb_switch *sw)
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{
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int start, size, nlc, ret, i;
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u32 desc;
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if (sw->generation < 2)
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return 0;
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ret = read_lc_desc(sw, &desc);
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if (ret)
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return ret;
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/* Figure out number of link controllers */
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nlc = desc & TB_LC_DESC_NLC_MASK;
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start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
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size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
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/* For each link controller set sleep bit */
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for (i = 0; i < nlc; i++) {
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unsigned int offset = sw->cap_lc + start + i * size;
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u32 ctrl;
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ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
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offset + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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ctrl |= TB_LC_SX_CTRL_SLP;
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ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,
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offset + TB_LC_SX_CTRL, 1);
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if (ret)
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return ret;
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}
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return 0;
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}
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/**
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* tb_lc_lane_bonding_possible() - Is lane bonding possible towards switch
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* @sw: Switch to check
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*
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* Checks whether conditions for lane bonding from parent to @sw are
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* possible.
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*/
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bool tb_lc_lane_bonding_possible(struct tb_switch *sw)
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{
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struct tb_port *up;
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int cap, ret;
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u32 val;
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if (sw->generation < 2)
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return false;
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up = tb_upstream_port(sw);
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cap = find_port_lc_cap(up);
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if (cap < 0)
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return false;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1);
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if (ret)
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return false;
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return !!(val & TB_LC_PORT_ATTR_BE);
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}
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static int tb_lc_dp_sink_from_port(const struct tb_switch *sw,
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struct tb_port *in)
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{
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struct tb_port *port;
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/* The first DP IN port is sink 0 and second is sink 1 */
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tb_switch_for_each_port(sw, port) {
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if (tb_port_is_dpin(port))
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return in != port;
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}
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return -EINVAL;
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}
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static int tb_lc_dp_sink_available(struct tb_switch *sw, int sink)
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{
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u32 val, alloc;
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int ret;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
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if (ret)
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return ret;
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/*
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* Sink is available for CM/SW to use if the allocation valie is
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* either 0 or 1.
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*/
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if (!sink) {
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alloc = val & TB_LC_SNK_ALLOCATION_SNK0_MASK;
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if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK0_CM)
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return 0;
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} else {
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alloc = (val & TB_LC_SNK_ALLOCATION_SNK1_MASK) >>
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TB_LC_SNK_ALLOCATION_SNK1_SHIFT;
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if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK1_CM)
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return 0;
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}
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return -EBUSY;
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}
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/**
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* tb_lc_dp_sink_query() - Is DP sink available for DP IN port
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* @sw: Switch whose DP sink is queried
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* @in: DP IN port to check
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*
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* Queries through LC SNK_ALLOCATION registers whether DP sink is available
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* for the given DP IN port or not.
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*/
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bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in)
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{
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int sink;
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/*
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* For older generations sink is always available as there is no
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* allocation mechanism.
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*/
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if (sw->generation < 3)
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return true;
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sink = tb_lc_dp_sink_from_port(sw, in);
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if (sink < 0)
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return false;
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return !tb_lc_dp_sink_available(sw, sink);
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}
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/**
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* tb_lc_dp_sink_alloc() - Allocate DP sink
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* @sw: Switch whose DP sink is allocated
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* @in: DP IN port the DP sink is allocated for
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*
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* Allocate DP sink for @in via LC SNK_ALLOCATION registers. If the
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* resource is available and allocation is successful returns %0. In all
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* other cases returs negative errno. In particular %-EBUSY is returned if
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* the resource was not available.
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*/
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int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in)
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{
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int ret, sink;
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u32 val;
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if (sw->generation < 3)
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return 0;
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sink = tb_lc_dp_sink_from_port(sw, in);
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if (sink < 0)
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return sink;
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ret = tb_lc_dp_sink_available(sw, sink);
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if (ret)
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return ret;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
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if (ret)
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return ret;
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if (!sink) {
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val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK;
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val |= TB_LC_SNK_ALLOCATION_SNK0_CM;
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} else {
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val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK;
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val |= TB_LC_SNK_ALLOCATION_SNK1_CM <<
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TB_LC_SNK_ALLOCATION_SNK1_SHIFT;
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}
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ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
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if (ret)
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return ret;
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tb_port_dbg(in, "sink %d allocated\n", sink);
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return 0;
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}
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/**
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* tb_lc_dp_sink_dealloc() - De-allocate DP sink
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* @sw: Switch whose DP sink is de-allocated
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* @in: DP IN port whose DP sink is de-allocated
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*
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* De-allocate DP sink from @in using LC SNK_ALLOCATION registers.
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*/
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int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in)
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{
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int ret, sink;
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u32 val;
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if (sw->generation < 3)
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return 0;
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sink = tb_lc_dp_sink_from_port(sw, in);
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if (sink < 0)
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return sink;
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/* Needs to be owned by CM/SW */
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ret = tb_lc_dp_sink_available(sw, sink);
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if (ret)
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return ret;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
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if (ret)
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return ret;
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if (!sink)
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val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK;
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else
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val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK;
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ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
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if (ret)
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return ret;
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tb_port_dbg(in, "sink %d de-allocated\n", sink);
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return 0;
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}
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/**
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* tb_lc_force_power() - Forces LC to be powered on
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* @sw: Thunderbolt switch
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*
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* This is useful to let authentication cycle pass even without
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* a Thunderbolt link present.
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*/
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int tb_lc_force_power(struct tb_switch *sw)
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{
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u32 in = 0xffff;
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return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1);
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}
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