152 lines
7.0 KiB
C
152 lines
7.0 KiB
C
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/*
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* PCI Register definitions for the MIPS System Controller.
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*
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* Copyright (C) 2004 MIPS Technologies, Inc. All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
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#define __ASM_MIPS_BOARDS_MSC01_IC_H
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/*****************************************************************************
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* Register offset addresses
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*****************************************************************************/
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#define MSC01_IC_RST_OFS 0x00008 /* Software reset */
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#define MSC01_IC_ENAL_OFS 0x00100 /* Int_in enable mask 31:0 */
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#define MSC01_IC_ENAH_OFS 0x00108 /* Int_in enable mask 63:32 */
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#define MSC01_IC_DISL_OFS 0x00120 /* Int_in disable mask 31:0 */
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#define MSC01_IC_DISH_OFS 0x00128 /* Int_in disable mask 63:32 */
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#define MSC01_IC_ISBL_OFS 0x00140 /* Raw int_in 31:0 */
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#define MSC01_IC_ISBH_OFS 0x00148 /* Raw int_in 63:32 */
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#define MSC01_IC_ISAL_OFS 0x00160 /* Masked int_in 31:0 */
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#define MSC01_IC_ISAH_OFS 0x00168 /* Masked int_in 63:32 */
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#define MSC01_IC_LVL_OFS 0x00180 /* Disable priority int_out */
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#define MSC01_IC_RAMW_OFS 0x00180 /* Shadow set RAM (EI) */
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#define MSC01_IC_OSB_OFS 0x00188 /* Raw int_out */
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#define MSC01_IC_OSA_OFS 0x00190 /* Masked int_out */
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#define MSC01_IC_GENA_OFS 0x00198 /* Global HW int enable */
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#define MSC01_IC_BASE_OFS 0x001a0 /* Base address of IC_VEC */
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#define MSC01_IC_VEC_OFS 0x001b0 /* Active int's vector address */
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#define MSC01_IC_EOI_OFS 0x001c0 /* Enable lower level ints */
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#define MSC01_IC_CFG_OFS 0x001c8 /* Configuration register */
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#define MSC01_IC_TRLD_OFS 0x001d0 /* Interval timer reload val */
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#define MSC01_IC_TVAL_OFS 0x001e0 /* Interval timer current val */
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#define MSC01_IC_TCFG_OFS 0x001f0 /* Interval timer config */
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#define MSC01_IC_SUP_OFS 0x00200 /* Set up int_in line 0 */
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#define MSC01_IC_ENA_OFS 0x00800 /* Int_in enable mask 63:0 */
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#define MSC01_IC_DIS_OFS 0x00820 /* Int_in disable mask 63:0 */
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#define MSC01_IC_ISB_OFS 0x00840 /* Raw int_in 63:0 */
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#define MSC01_IC_ISA_OFS 0x00860 /* Masked int_in 63:0 */
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/*****************************************************************************
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* Register field encodings
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*****************************************************************************/
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#define MSC01_IC_RST_RST_SHF 0
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#define MSC01_IC_RST_RST_MSK 0x00000001
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#define MSC01_IC_RST_RST_BIT MSC01_IC_RST_RST_MSK
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#define MSC01_IC_LVL_LVL_SHF 0
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#define MSC01_IC_LVL_LVL_MSK 0x000000ff
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#define MSC01_IC_LVL_SPUR_SHF 16
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#define MSC01_IC_LVL_SPUR_MSK 0x00010000
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#define MSC01_IC_LVL_SPUR_BIT MSC01_IC_LVL_SPUR_MSK
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#define MSC01_IC_RAMW_RIPL_SHF 0
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#define MSC01_IC_RAMW_RIPL_MSK 0x0000003f
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#define MSC01_IC_RAMW_DATA_SHF 6
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#define MSC01_IC_RAMW_DATA_MSK 0x00000fc0
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#define MSC01_IC_RAMW_ADDR_SHF 25
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#define MSC01_IC_RAMW_ADDR_MSK 0x7e000000
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#define MSC01_IC_RAMW_READ_SHF 31
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#define MSC01_IC_RAMW_READ_MSK 0x80000000
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#define MSC01_IC_RAMW_READ_BIT MSC01_IC_RAMW_READ_MSK
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#define MSC01_IC_OSB_OSB_SHF 0
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#define MSC01_IC_OSB_OSB_MSK 0x000000ff
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#define MSC01_IC_OSA_OSA_SHF 0
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#define MSC01_IC_OSA_OSA_MSK 0x000000ff
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#define MSC01_IC_GENA_GENA_SHF 0
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#define MSC01_IC_GENA_GENA_MSK 0x00000001
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#define MSC01_IC_GENA_GENA_BIT MSC01_IC_GENA_GENA_MSK
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#define MSC01_IC_CFG_DIS_SHF 0
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#define MSC01_IC_CFG_DIS_MSK 0x00000001
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#define MSC01_IC_CFG_DIS_BIT MSC01_IC_CFG_DIS_MSK
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#define MSC01_IC_CFG_SHFT_SHF 8
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#define MSC01_IC_CFG_SHFT_MSK 0x00000f00
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#define MSC01_IC_TCFG_ENA_SHF 0
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#define MSC01_IC_TCFG_ENA_MSK 0x00000001
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#define MSC01_IC_TCFG_ENA_BIT MSC01_IC_TCFG_ENA_MSK
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#define MSC01_IC_TCFG_INT_SHF 8
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#define MSC01_IC_TCFG_INT_MSK 0x00000100
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#define MSC01_IC_TCFG_INT_BIT MSC01_IC_TCFG_INT_MSK
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#define MSC01_IC_TCFG_EDGE_SHF 16
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#define MSC01_IC_TCFG_EDGE_MSK 0x00010000
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#define MSC01_IC_TCFG_EDGE_BIT MSC01_IC_TCFG_EDGE_MSK
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#define MSC01_IC_SUP_PRI_SHF 0
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#define MSC01_IC_SUP_PRI_MSK 0x00000007
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#define MSC01_IC_SUP_EDGE_SHF 8
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#define MSC01_IC_SUP_EDGE_MSK 0x00000100
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#define MSC01_IC_SUP_EDGE_BIT MSC01_IC_SUP_EDGE_MSK
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#define MSC01_IC_SUP_STEP 8
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/*
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* MIPS System controller interrupt register base.
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*
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* FIXME - are these macros specific to Malta and co or to the MSC? If the
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* latter, they should be moved elsewhere.
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*/
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#define MIPS_MSC01_IC_REG_BASE 0x1bc40000
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/*****************************************************************************
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* Absolute register addresses
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*****************************************************************************/
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#define MSC01_IC_RST (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
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#define MSC01_IC_ENAL (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
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#define MSC01_IC_ENAH (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
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#define MSC01_IC_DISL (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
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#define MSC01_IC_DISH (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
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#define MSC01_IC_ISBL (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
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#define MSC01_IC_ISBH (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
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#define MSC01_IC_ISAL (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
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#define MSC01_IC_ISAH (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
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#define MSC01_IC_LVL (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
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#define MSC01_IC_RAMW (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
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#define MSC01_IC_OSB (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
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#define MSC01_IC_OSA (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
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#define MSC01_IC_GENA (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
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#define MSC01_IC_BASE (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
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#define MSC01_IC_VEC (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
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#define MSC01_IC_EOI (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
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#define MSC01_IC_CFG (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
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#define MSC01_IC_TRLD (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
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#define MSC01_IC_TVAL (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
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#define MSC01_IC_TCFG (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
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#define MSC01_IC_SUP (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
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#define MSC01_IC_ENA (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
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#define MSC01_IC_DIS (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
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#define MSC01_IC_ISB (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
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#define MSC01_IC_ISA (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
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/*
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* Soc-it interrupts are configurable.
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* Every board describes its IRQ mapping with this table.
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*/
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typedef struct msc_irqmap {
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int im_irq;
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int im_type;
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int im_lvl;
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} msc_irqmap_t;
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/* im_type */
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#define MSC01_IRQ_LEVEL 0
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#define MSC01_IRQ_EDGE 1
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extern void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq);
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extern void ll_msc_irq(struct pt_regs *regs);
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#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
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