2019-10-20 22:43:14 +08:00
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#
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# Loongson Processors' Support
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#
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# Only gcc >= 4.4 have Loongson specific support
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cflags-$(CONFIG_CPU_LOONGSON2EF) += -Wa,--trap
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cflags-$(CONFIG_CPU_LOONGSON2E) += \
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$(call cc-option,-march=loongson2e,-march=r4600)
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cflags-$(CONFIG_CPU_LOONGSON2F) += \
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$(call cc-option,-march=loongson2f,-march=r4600)
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MIPS: Loongson-2EF: disable fix-loongson3-llsc in compiler
Firstly, Loongson-2EF support ll/sc instructions, but
doesn't need fix-loongson3-llsc compile option.
Secondly, fix-loongson3-llsc will cause kernel startup
fail at futex_init, because compiler will add 'sync' before
'll', which will affect __ex_table.
futex_init will pass NULL uaddr parameter to
futex_atomic_cmpxchg_inatomic.
futex_atomic_cmpxchg_inatomic will access uaddr directly,
which will cause page fault exception, the exception should be
handled by __ex_table's nextinsn if the exception insn exsit in
__ex_table. Because __ex_table is affected by compiler,
the exception can not be handled, and
futex_atomic_cmpxchg_inatomic will crash.
Error code as below:
__ex_table.insn = 1b, which is 'sync' compiled with
fix-loongson3-llsc, but the actual exception instrction is ll.
So, do_page_fault will not find the correct inst in __ex_table, and
can not handle this exception.
"1: "user_ll("%1", "%3")" \n"
" bne %1, %z4, 3f \n"
" .set pop \n"
" move $1, %z5 \n"
" .set "MIPS_ISA_ARCH_LEVEL" \n"
"2: "user_sc("$1", "%2")" \n"
" beqz $1, 1b \n"
"3: " __SYNC_ELSE(full, loongson3_war, __WEAK_LLSC_MB) "\n"
" .insn \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
"4: li %0, %6 \n"
" j 3b \n"
" .previous \n"
" .section __ex_table,\"a\" \n"
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous
Signed-off-by: Lichao Liu <liulichao@loongson.cn>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2020-06-11 17:59:24 +08:00
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#
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# Some versions of binutils, not currently mainline as of 2019/02/04, support
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# an -mfix-loongson3-llsc flag which emits a sync prior to each ll instruction
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# to work around a CPU bug (see __SYNC_loongson3_war in asm/sync.h for a
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# description).
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#
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# We disable this in order to prevent the assembler meddling with the
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# instruction that labels refer to, ie. if we label an ll instruction:
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#
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# 1: ll v0, 0(a0)
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#
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# ...then with the assembler fix applied the label may actually point at a sync
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# instruction inserted by the assembler, and if we were using the label in an
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# exception table the table would no longer contain the address of the ll
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# instruction.
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#
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# Avoid this by explicitly disabling that assembler behaviour. If upstream
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# binutils does not merge support for the flag then we can revisit & remove
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# this later - for now it ensures vendor toolchains don't cause problems.
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#
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cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call as-option,-Wa$(comma)-mno-fix-loongson3-llsc,)
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2019-10-20 22:43:14 +08:00
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# Enable the workarounds for Loongson2f
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ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS
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ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-nop,),)
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$(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-nop)
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else
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cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-nop
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endif
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ifeq ($(call as-option,-Wa$(comma)-mfix-loongson2f-jump,),)
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$(error only binutils >= 2.20.2 have needed option -mfix-loongson2f-jump)
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else
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cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa$(comma)-mfix-loongson2f-jump
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endif
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endif
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2020-09-23 18:33:12 +08:00
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# Some -march= flags enable MMI instructions, and GCC complains about that
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# support being enabled alongside -msoft-float. Thus explicitly disable MMI.
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cflags-y += $(call cc-option,-mno-loongson-mmi)
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2019-10-20 22:43:14 +08:00
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#
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# Loongson Machines' Support
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#
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cflags-$(CONFIG_MACH_LOONGSON2EF) += -I$(srctree)/arch/mips/include/asm/mach-loongson2ef -mno-branch-likely
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load-$(CONFIG_LEMOTE_FULOONG2E) += 0xffffffff80100000
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load-$(CONFIG_LEMOTE_MACH2F) += 0xffffffff80200000
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