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Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu

Browse Source 
Pull m68knommu updates from Greg Ungerer:
 "There are two sets of changes in this pull.

  The largest is the addition of the ColdFire platform side i2c support
  (the IO addressing, setup and clock definitions). The i2c hardware
  module itself is driven by the kernels existing iMX i2c driver.

  The other change is the addition of support for the Amcore board"

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu:
  m68knommu: AMCORE board, add iMX i2c support
  m68k: add Sysam AMCORE open board support
  m68knommu: platform support for i2c devices on ColdFire SoC
This commit is contained in:
Linus Torvalds 2016-12-12 08:44:23 -08:00
commit 0261b5d3a6
26 changed files with 713 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/m68k/Kconfig.machine
View File

@ -259,6 +259,12 @@ config M5407C3
help
Support for the Motorola M5407C3 board.
config AMCORE
bool "Sysam AMCORE board support"
depends on M5307
help
Support for the Sysam AMCORE open-hardware generic board.
config FIREBEE
bool "FireBee board support"
depends on M547x

1
arch/m68k/coldfire/Makefile
View File

@ -34,6 +34,7 @@ obj-$(CONFIG_NETtel) += nettel.o
obj-$(CONFIG_CLEOPATRA) += nettel.o
obj-$(CONFIG_FIREBEE) += firebee.o
obj-$(CONFIG_MCF8390) += mcf8390.o
obj-$(CONFIG_AMCORE) += amcore.o
obj-$(CONFIG_PCI) += pci.o

156
arch/m68k/coldfire/amcore.c Normal file
View File

@ -0,0 +1,156 @@
/*
* amcore.c -- Support for Sysam AMCORE open board
*
* (C) Copyright 2016, Angelo Dureghello <angelo@sysam.it>
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/dm9000.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/map.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
#include <asm/io.h>
#if IS_ENABLED(CONFIG_DM9000)
#define DM9000_IRQ 25
#define DM9000_ADDR 0x30000000
/*
* DEVICES and related device RESOURCES
*/
static struct resource dm9000_resources[] = {
/* physical address of the address register (CMD [A2] to 0)*/
[0] = {
.start = DM9000_ADDR,
.end = DM9000_ADDR,
.flags = IORESOURCE_MEM,
},
/*
* physical address of the data register (CMD [A2] to 1),
* driver wants a range >=4 to assume a 32bit data bus
*/
[1] = {
.start = DM9000_ADDR + 4,
.end = DM9000_ADDR + 7,
.flags = IORESOURCE_MEM,
},
/* IRQ line the device's interrupt pin is connected to */
[2] = {
.start = DM9000_IRQ,
.end = DM9000_IRQ,
.flags = IORESOURCE_IRQ,
},
};
static struct dm9000_plat_data dm9000_platdata = {
.flags = DM9000_PLATF_32BITONLY,
};
static struct platform_device dm9000_device = {
.name = "dm9000",
.id = 0,
.num_resources = ARRAY_SIZE(dm9000_resources),
.resource = dm9000_resources,
.dev = {
.platform_data = &dm9000_platdata,
}
};
#endif
static void __init dm9000_pre_init(void)
{
/* Set the dm9000 interrupt to be auto-vectored */
mcf_autovector(DM9000_IRQ);
}
/*
* Partitioning of parallel NOR flash (39VF3201B)
*/
static struct mtd_partition amcore_partitions[] = {
{
.name = "U-Boot (128K)",
.size = 0x20000,
.offset = 0x0
},
{
.name = "Kernel+ROMfs (2994K)",
.size = 0x2E0000,
.offset = MTDPART_OFS_APPEND
},
{
.name = "Flash Free Space (1024K)",
.size = MTDPART_SIZ_FULL,
.offset = MTDPART_OFS_APPEND
}
};
static struct physmap_flash_data flash_data = {
.parts = amcore_partitions,
.nr_parts = ARRAY_SIZE(amcore_partitions),
.width = 2,
};
static struct resource flash_resource = {
.start = 0xffc00000,
.end = 0xffffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = -1,
.resource = &flash_resource,
.num_resources = 1,
.dev = {
.platform_data = &flash_data,
},
};
static struct platform_device rtc_device = {
.name = "rtc-ds1307",
.id = -1,
};
static struct i2c_board_info amcore_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("ds1338", 0x68),
},
};
static struct platform_device *amcore_devices[] __initdata = {
#if IS_ENABLED(CONFIG_DM9000)
&dm9000_device,
#endif
&flash_device,
&rtc_device,
};
static int __init init_amcore(void)
{
#if IS_ENABLED(CONFIG_DM9000)
dm9000_pre_init();
#endif
/* Add i2c RTC Dallas chip supprt */
i2c_register_board_info(0, amcore_i2c_info,
ARRAY_SIZE(amcore_i2c_info));
platform_add_devices(amcore_devices, ARRAY_SIZE(amcore_devices));
return 0;
}
arch_initcall(init_amcore);

159
arch/m68k/coldfire/device.c
View File

@ -327,6 +327,147 @@ static struct platform_device mcf_qspi = {
};
#endif /* IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI) */
#if IS_ENABLED(CONFIG_I2C_IMX)
static struct resource mcf_i2c0_resources[] = {
{
.start = MCFI2C_BASE0,
.end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C0,
.end = MCF_IRQ_I2C0,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c0 = {
.name = "imx1-i2c",
.id = 0,
.num_resources = ARRAY_SIZE(mcf_i2c0_resources),
.resource = mcf_i2c0_resources,
};
#ifdef MCFI2C_BASE1
static struct resource mcf_i2c1_resources[] = {
{
.start = MCFI2C_BASE1,
.end = MCFI2C_BASE1 + MCFI2C_SIZE1 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C1,
.end = MCF_IRQ_I2C1,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c1 = {
.name = "imx1-i2c",
.id = 1,
.num_resources = ARRAY_SIZE(mcf_i2c1_resources),
.resource = mcf_i2c1_resources,
};
#endif /* MCFI2C_BASE1 */
#ifdef MCFI2C_BASE2
static struct resource mcf_i2c2_resources[] = {
{
.start = MCFI2C_BASE2,
.end = MCFI2C_BASE2 + MCFI2C_SIZE2 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C2,
.end = MCF_IRQ_I2C2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c2 = {
.name = "imx1-i2c",
.id = 2,
.num_resources = ARRAY_SIZE(mcf_i2c2_resources),
.resource = mcf_i2c2_resources,
};
#endif /* MCFI2C_BASE2 */
#ifdef MCFI2C_BASE3
static struct resource mcf_i2c3_resources[] = {
{
.start = MCFI2C_BASE3,
.end = MCFI2C_BASE3 + MCFI2C_SIZE3 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C3,
.end = MCF_IRQ_I2C3,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c3 = {
.name = "imx1-i2c",
.id = 3,
.num_resources = ARRAY_SIZE(mcf_i2c3_resources),
.resource = mcf_i2c3_resources,
};
#endif /* MCFI2C_BASE3 */
#ifdef MCFI2C_BASE4
static struct resource mcf_i2c4_resources[] = {
{
.start = MCFI2C_BASE4,
.end = MCFI2C_BASE4 + MCFI2C_SIZE4 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C4,
.end = MCF_IRQ_I2C4,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c4 = {
.name = "imx1-i2c",
.id = 4,
.num_resources = ARRAY_SIZE(mcf_i2c4_resources),
.resource = mcf_i2c4_resources,
};
#endif /* MCFI2C_BASE4 */
#ifdef MCFI2C_BASE5
static struct resource mcf_i2c5_resources[] = {
{
.start = MCFI2C_BASE5,
.end = MCFI2C_BASE5 + MCFI2C_SIZE5 - 1,
.flags = IORESOURCE_MEM,
},
{
.start = MCF_IRQ_I2C5,
.end = MCF_IRQ_I2C5,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mcf_i2c5 = {
.name = "imx1-i2c",
.id = 5,
.num_resources = ARRAY_SIZE(mcf_i2c5_resources),
.resource = mcf_i2c5_resources,
};
#endif /* MCFI2C_BASE5 */
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
static struct platform_device *mcf_devices[] __initdata = {
&mcf_uart,
#if IS_ENABLED(CONFIG_FEC)
@ -338,6 +479,24 @@ static struct platform_device *mcf_devices[] __initdata = {
#if IS_ENABLED(CONFIG_SPI_COLDFIRE_QSPI)
&mcf_qspi,
#endif
#if IS_ENABLED(CONFIG_I2C_IMX)
&mcf_i2c0,
#ifdef MCFI2C_BASE1
&mcf_i2c1,
#endif
#ifdef MCFI2C_BASE2
&mcf_i2c2,
#endif
#ifdef MCFI2C_BASE3
&mcf_i2c3,
#endif
#ifdef MCFI2C_BASE4
&mcf_i2c4,
#endif
#ifdef MCFI2C_BASE5
&mcf_i2c5,
#endif
#endif
};
/*

12
arch/m68k/coldfire/m5206.c
View File

@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -34,11 +35,21 @@ struct clk *mcf_clks[] = {
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
};
/***************************************************************************/
static void __init m5206_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel)
@ -53,6 +64,7 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(25, MCFINTC_EINT1);
mcf_mapirq2imr(28, MCFINTC_EINT4);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5206_i2c_init();
}
/***************************************************************************/

24
arch/m68k/coldfire/m520x.c
View File

@ -28,7 +28,7 @@ DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
@ -53,7 +53,7 @@ struct clk *mcf_clks[] = {
&__clk_0_17, /* edma */
&__clk_0_18, /* intc.0 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
@ -71,7 +71,7 @@ struct clk *mcf_clks[] = {
&__clk_0_40, /* sys.0 */
&__clk_0_41, /* gpio.0 */
&__clk_0_42, /* sdram.0 */
NULL,
NULL,
};
static struct clk * const enable_clks[] __initconst = {
@ -94,7 +94,7 @@ static struct clk * const enable_clks[] __initconst = {
static struct clk * const disable_clks[] __initconst = {
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_28, /* mcftmr.0 */
&__clk_0_29, /* mcftmr.1 */
@ -133,6 +133,21 @@ static void __init m520x_qspi_init(void)
/***************************************************************************/
static void __init m520x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u8 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCF_GPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCF_GPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m520x_uarts_init(void)
{
u16 par;
@ -175,6 +190,7 @@ void __init config_BSP(char *commandp, int size)
m520x_uarts_init();
m520x_fec_init();
m520x_qspi_init();
m520x_i2c_init();
}
/***************************************************************************/

18
arch/m68k/coldfire/m523x.c
View File

@ -34,6 +34,7 @@ DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -47,6 +48,7 @@ struct clk *mcf_clks[] = {
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
};
@ -68,6 +70,21 @@ static void __init m523x_qspi_init(void)
/***************************************************************************/
static void __init m523x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u8 par;
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m523x_fec_init(void)
{
/* Set multi-function pins to ethernet use */
@ -81,6 +98,7 @@ void __init config_BSP(char *commandp, int size)
mach_sched_init = hw_timer_init;
m523x_fec_init();
m523x_qspi_init();
m523x_i2c_init();
}
/***************************************************************************/

25
arch/m68k/coldfire/m5249.c
View File

@ -27,6 +27,8 @@ DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -36,6 +38,8 @@ struct clk *mcf_clks[] = {
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
};
@ -85,6 +89,26 @@ static void __init m5249_qspi_init(void)
/***************************************************************************/
static void __init m5249_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
r = readl(MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* CONFIG_I2C_IMX */
}
/***************************************************************************/
#ifdef CONFIG_M5249C3
static void __init m5249_smc91x_init(void)
@ -111,6 +135,7 @@ void __init config_BSP(char *commandp, int size)
m5249_smc91x_init();
#endif
m5249_qspi_init();
m5249_i2c_init();
}
/***************************************************************************/

10
arch/m68k/coldfire/m525x.c
View File

@ -27,6 +27,8 @@ DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c1, "imx1-i2c.1", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -36,6 +38,8 @@ struct clk *mcf_clks[] = {
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfqspi0,
&clk_mcfi2c0,
&clk_mcfi2c1,
NULL
};
@ -59,12 +63,12 @@ static void __init m525x_qspi_init(void)
static void __init m525x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_COLDFIRE)
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* first I2C controller uses regular irq setup */
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
/* second I2C controller is completely different */
@ -72,7 +76,7 @@ static void __init m525x_i2c_init(void)
r &= ~MCFINTC2_INTPRI_BITS(0xf, MCF_IRQ_I2C1);
r |= MCFINTC2_INTPRI_BITS(0x5, MCF_IRQ_I2C1);
writel(r, MCFINTC2_INTPRI_REG(MCF_IRQ_I2C1));
#endif /* IS_ENABLED(CONFIG_I2C_COLDFIRE) */
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/

28
arch/m68k/coldfire/m527x.c
View File

@ -36,6 +36,7 @@ DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(fec1, "fec.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -50,6 +51,7 @@ struct clk *mcf_clks[] = {
&clk_mcfqspi0,
&clk_fec0,
&clk_fec1,
&clk_mcfi2c0,
NULL
};
@ -76,6 +78,31 @@ static void __init m527x_qspi_init(void)
/***************************************************************************/
static void __init m527x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
#if defined(CONFIG_M5271)
u8 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readb(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writeb(par, MCFGPIO_PAR_FECI2C);
#elif defined(CONFIG_M5275)
u16 par;
/* setup Port FECI2C Pin Assignment Register for I2C */
/* set PAR_SCL to SCL and PAR_SDA to SDA */
par = readw(MCFGPIO_PAR_FECI2C);
par |= 0x0f;
writew(par, MCFGPIO_PAR_FECI2C);
#endif
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m527x_uarts_init(void)
{
u16 sepmask;
@ -122,6 +149,7 @@ void __init config_BSP(char *commandp, int size)
m527x_uarts_init();
m527x_fec_init();
m527x_qspi_init();
m527x_i2c_init();
}
/***************************************************************************/

18
arch/m68k/coldfire/m528x.c
View File

@ -36,6 +36,7 @@ DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfqspi0, "mcfqspi.0", MCF_BUSCLK);
DEFINE_CLK(fec0, "fec.0", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -49,6 +50,7 @@ struct clk *mcf_clks[] = {
&clk_mcfuart2,
&clk_mcfqspi0,
&clk_fec0,
&clk_mcfi2c0,
NULL
};
@ -64,6 +66,21 @@ static void __init m528x_qspi_init(void)
/***************************************************************************/
static void __init m528x_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u16 paspar;
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
paspar = readw(MCFGPIO_PASPAR);
paspar |= 0xF;
writew(paspar, MCFGPIO_PASPAR);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m528x_uarts_init(void)
{
u8 port;
@ -127,6 +144,7 @@ void __init config_BSP(char *commandp, int size)
m528x_uarts_init();
m528x_fec_init();
m528x_qspi_init();
m528x_i2c_init();
}
/***************************************************************************/

14
arch/m68k/coldfire/m5307.c
View File

@ -35,6 +35,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -43,11 +44,23 @@ struct clk *mcf_clks[] = {
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
};
/***************************************************************************/
static void __init m5307_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
#if defined(CONFIG_NETtel) || \
@ -73,6 +86,7 @@ void __init config_BSP(char *commandp, int size)
*/
wdebug(MCFDEBUG_CSR, MCFDEBUG_CSR_PSTCLK);
#endif
m5307_i2c_init();
}
/***************************************************************************/

20
arch/m68k/coldfire/m53xx.c
View File

@ -38,7 +38,7 @@ DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
@ -77,7 +77,7 @@ struct clk *mcf_clks[] = {
&__clk_0_18, /* intc.0 */
&__clk_0_19, /* intc.1 */
&__clk_0_21, /* iack.0 */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_24, /* mcfuart.0 */
&__clk_0_25, /* mcfuart.1 */
@ -133,7 +133,7 @@ static struct clk * const disable_clks[] __initconst = {
&__clk_0_8, /* mcfcan.0 */
&__clk_0_12, /* fec.0 */
&__clk_0_17, /* edma */
&__clk_0_22, /* mcfi2c.0 */
&__clk_0_22, /* imx1-i2c.0 */
&__clk_0_23, /* mcfqspi.0 */
&__clk_0_30, /* mcftmr.2 */
&__clk_0_31, /* mcftmr.3 */
@ -176,6 +176,19 @@ static void __init m53xx_qspi_init(void)
/***************************************************************************/
static void __init m53xx_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
/* setup Port AS Pin Assignment Register for I2C */
/* set PASPA0 to SCL and PASPA1 to SDA */
u8 r = readb(MCFGPIO_PAR_FECI2C);
r |= 0x0f;
writeb(r, MCFGPIO_PAR_FECI2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void __init m53xx_uarts_init(void)
{
/* UART GPIO initialization */
@ -218,6 +231,7 @@ void __init config_BSP(char *commandp, int size)
m53xx_uarts_init();
m53xx_fec_init();
m53xx_qspi_init();
m53xx_i2c_init();
#ifdef CONFIG_BDM_DISABLE
/*

14
arch/m68k/coldfire/m5407.c
View File

@ -26,6 +26,7 @@ DEFINE_CLK(mcftmr0, "mcftmr.0", MCF_BUSCLK);
DEFINE_CLK(mcftmr1, "mcftmr.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -34,11 +35,23 @@ struct clk *mcf_clks[] = {
&clk_mcftmr1,
&clk_mcfuart0,
&clk_mcfuart1,
&clk_mcfi2c0,
NULL
};
/***************************************************************************/
static void __init m5407_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
writeb(MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL5 | MCFSIM_ICR_PRI0,
MCFSIM_I2CICR);
mcf_mapirq2imr(MCF_IRQ_I2C0, MCFINTC_I2C);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
void __init config_BSP(char *commandp, int size)
{
mach_sched_init = hw_timer_init;
@ -48,6 +61,7 @@ void __init config_BSP(char *commandp, int size)
mcf_mapirq2imr(27, MCFINTC_EINT3);
mcf_mapirq2imr(29, MCFINTC_EINT5);
mcf_mapirq2imr(31, MCFINTC_EINT7);
m5407_i2c_init();
}
/***************************************************************************/

12
arch/m68k/coldfire/m5441x.c
View File

@ -19,13 +19,13 @@
DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
DEFINE_CLK(0, "mcfcan.1", 9, MCF_CLK);
DEFINE_CLK(0, "mcfi2c.1", 14, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.1", 14, MCF_CLK);
DEFINE_CLK(0, "mcfdspi.1", 15, MCF_CLK);
DEFINE_CLK(0, "edma", 17, MCF_CLK);
DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
DEFINE_CLK(0, "intc.2", 20, MCF_CLK);
DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
DEFINE_CLK(0, "mcfdspi.0", 23, MCF_CLK);
DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
@ -59,10 +59,10 @@ DEFINE_CLK(0, "switch.1", 56, MCF_CLK);
DEFINE_CLK(0, "nand.0", 63, MCF_CLK);
DEFINE_CLK(1, "mcfow.0", 2, MCF_CLK);
DEFINE_CLK(1, "mcfi2c.2", 4, MCF_CLK);
DEFINE_CLK(1, "mcfi2c.3", 5, MCF_CLK);
DEFINE_CLK(1, "mcfi2c.4", 6, MCF_CLK);
DEFINE_CLK(1, "mcfi2c.5", 7, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.2", 4, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.3", 5, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.4", 6, MCF_CLK);
DEFINE_CLK(1, "imx1-i2c.5", 7, MCF_CLK);
DEFINE_CLK(1, "mcfuart.4", 24, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.5", 25, MCF_BUSCLK);
DEFINE_CLK(1, "mcfuart.6", 26, MCF_BUSCLK);

17
arch/m68k/coldfire/m54xx.c
View File

@ -37,6 +37,7 @@ DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
struct clk *mcf_clks[] = {
&clk_pll,
@ -47,6 +48,7 @@ struct clk *mcf_clks[] = {
&clk_mcfuart1,
&clk_mcfuart2,
&clk_mcfuart3,
&clk_mcfi2c0,
NULL
};
@ -65,6 +67,20 @@ static void __init m54xx_uarts_init(void)
/***************************************************************************/
static void __init m54xx_i2c_init(void)
{
#if IS_ENABLED(CONFIG_I2C_IMX)
u32 r;
/* set the fec/i2c/irq pin assignment register for i2c */
r = readl(MCF_PAR_FECI2CIRQ);
r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
writel(r, MCF_PAR_FECI2CIRQ);
#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
}
/***************************************************************************/
static void mcf54xx_reset(void)
{
/* disable interrupts and enable the watchdog */
@ -86,6 +102,7 @@ void __init config_BSP(char *commandp, int size)
mach_reset = mcf54xx_reset;
mach_sched_init = hw_timer_init;
m54xx_uarts_init();
m54xx_i2c_init();
}
/***************************************************************************/

118
arch/m68k/configs/amcore_defconfig Normal file
View File

@ -0,0 +1,118 @@
CONFIG_LOCALVERSION="amcore-001"
CONFIG_DEFAULT_HOSTNAME="amcore"
CONFIG_SYSVIPC=y
# CONFIG_FHANDLE is not set
# CONFIG_USELIB is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_NAMESPACES=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
# CONFIG_AIO is not set
# CONFIG_ADVISE_SYSCALLS is not set
# CONFIG_MEMBARRIER is not set
CONFIG_EMBEDDED=y
# CONFIG_VM_EVENT_COUNTERS is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_MMU is not set
CONFIG_M5307=y
CONFIG_AMCORE=y
CONFIG_UBOOT=y
CONFIG_RAMSIZE=0x1000000
CONFIG_KERNELBASE=0x20000
CONFIG_NOMMU_INITIAL_TRIM_EXCESS=0
CONFIG_BINFMT_FLAT=y
# CONFIG_COREDUMP is not set
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
# CONFIG_UEVENT_HELPER is not set
CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y
# CONFIG_ALLOW_DEV_COREDUMP is not set
CONFIG_CONNECTOR=y
CONFIG_MTD=y
CONFIG_MTD_BLOCK=y
CONFIG_MTD_CFI=y
CONFIG_MTD_JEDECPROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_LE_BYTE_SWAP=y
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_CFI_I2 is not set
CONFIG_MTD_CFI_AMDSTD=y
CONFIG_MTD_CFI_STAA=y
CONFIG_MTD_ROM=y
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_UCLINUX=y
CONFIG_MTD_PLATRAM=y
CONFIG_BLK_DEV_RAM=y
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_DM9000=y
# CONFIG_NET_VENDOR_EZCHIP is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
# CONFIG_NET_VENDOR_MICREL is not set
# CONFIG_NET_VENDOR_NATSEMI is not set
# CONFIG_NET_VENDOR_NETRONOME is not set
# CONFIG_NET_VENDOR_QUALCOMM is not set
# CONFIG_NET_VENDOR_RENESAS is not set
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SMSC is not set
# CONFIG_NET_VENDOR_STMICRO is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_VIA is not set
# CONFIG_NET_VENDOR_WIZNET is not set
# CONFIG_WLAN is not set
# CONFIG_INPUT is not set
# CONFIG_SERIO is not set
# CONFIG_VT is not set
# CONFIG_UNIX98_PTYS is not set
# CONFIG_DEVMEM is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_MCF=y
CONFIG_SERIAL_MCF_BAUDRATE=115200
CONFIG_SERIAL_MCF_CONSOLE=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
# CONFIG_I2C_COMPAT is not set
CONFIG_I2C_CHARDEV=y
# CONFIG_I2C_HELPER_AUTO is not set
CONFIG_I2C_IMX=y
CONFIG_PPS=y
# CONFIG_HWMON is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
# CONFIG_RTC_SYSTOHC is not set
CONFIG_RTC_DRV_DS1307=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
CONFIG_FSCACHE=y
# CONFIG_PROC_SYSCTL is not set
CONFIG_JFFS2_FS=y
CONFIG_ROMFS_FS=y
CONFIG_ROMFS_BACKED_BY_BOTH=y
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_PRINTK_TIME=y
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
CONFIG_PANIC_ON_OOPS=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_CRYPTO_ECHAINIV is not set
CONFIG_CRYPTO_ANSI_CPRNG=y
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC16=y

8
arch/m68k/include/asm/m5206sim.h
View File

@ -110,6 +110,7 @@
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
@ -138,6 +139,7 @@
#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
#define MCFSIM_I2CICR MCFSIM_ICR11 /* I2C ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
#ifdef CONFIG_M5206e
@ -145,5 +147,11 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
#endif
/*
* I2C Controller
*/
#define MCFI2C_BASE0 (MCF_MBAR + 0x1e0)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m5206sim_h */

8
arch/m68k/include/asm/m520xsim.h
View File

@ -50,6 +50,7 @@
#define MCFINT_UART0 26 /* Interrupt number for UART0 */
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_I2C0 30 /* Interrupt number for I2C */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
@ -67,6 +68,7 @@
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
/*
* SDRAM configuration registers.
*/
@ -200,5 +202,11 @@
#define MCFPM_PPMLR0 0xfc040034
#define MCFPM_LPCR 0xfc0a0007
/*
* I2C module.
*/
#define MCFI2C_BASE0 0xFC058000
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m520xsim_h */

10
arch/m68k/include/asm/m523xsim.h
View File

@ -37,7 +37,8 @@
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_I2C0 17 /* Interrupt number for I2C */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
#define MCFINT_FECENTC0 29 /* Interrupt number for FEC */
@ -53,6 +54,7 @@
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
/*
* SDRAM configuration registers.
@ -208,5 +210,11 @@
#define MCFDMA_BASE2 (MCF_IPSBAR + 0x180)
#define MCFDMA_BASE3 (MCF_IPSBAR + 0x1C0)
/*
* I2C module.
*/
#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m523xsim_h */

8
arch/m68k/include/asm/m527xsim.h
View File

@ -37,6 +37,7 @@
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_I2C0 17 /* Interrupt number for I2C */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC0 */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC0 */
@ -61,6 +62,7 @@
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
/*
* SDRAM configuration registers.
@ -353,5 +355,11 @@
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* I2C module.
*/
#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m527xsim_h */

9
arch/m68k/include/asm/m528xsim.h
View File

@ -37,6 +37,7 @@
#define MCFINT_UART0 13 /* Interrupt number for UART0 */
#define MCFINT_UART1 14 /* Interrupt number for UART1 */
#define MCFINT_UART2 15 /* Interrupt number for UART2 */
#define MCFINT_I2C0 17 /* Interrupt number for I2C */
#define MCFINT_QSPI 18 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 23 /* Interrupt number for FEC */
#define MCFINT_FECTX0 27 /* Interrupt number for FEC */
@ -53,6 +54,8 @@
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_IRQ_PIT1 (MCFINT_VECBASE + MCFINT_PIT1)
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
/*
* SDRAM configuration registers.
*/
@ -242,5 +245,11 @@
#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
/*
* I2C module
*/
#define MCFI2C_BASE0 (MCF_IPSBAR + 0x300)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m528xsim_h */

9
arch/m68k/include/asm/m5307sim.h
View File

@ -148,6 +148,7 @@
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
@ -155,7 +156,6 @@
#define MCFSIM_DMA2ICR MCFSIM_ICR8 /* DMA 2 ICR */
#define MCFSIM_DMA3ICR MCFSIM_ICR9 /* DMA 3 ICR */
/*
* Some symbol defines for the Parallel Port Pin Assignment Register
*/
@ -174,10 +174,17 @@
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/*
* I2C module
*/
#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m5307sim_h */

8
arch/m68k/include/asm/m53xxsim.h
View File

@ -19,6 +19,7 @@
#define MCFINT_UART0 26 /* Interrupt number for UART0 */
#define MCFINT_UART1 27 /* Interrupt number for UART1 */
#define MCFINT_UART2 28 /* Interrupt number for UART2 */
#define MCFINT_I2C0 30 /* Interrupt number for I2C */
#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
#define MCFINT_FECRX0 36 /* Interrupt number for FEC */
#define MCFINT_FECTX0 40 /* Interrupt number for FEC */
@ -32,6 +33,7 @@
#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + MCFINT_I2C0)
#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
#define MCF_WTM_WCR 0xFC098000
@ -1237,5 +1239,11 @@
#define MCFEPORT_EPPDR (0xFC094005)
#define MCFEPORT_EPFR (0xFC094006)
/*
* I2C Module
*/
#define MCFI2C_BASE0 (0xFc058000)
#define MCFI2C_SIZE0 0x40
/********************************************************************/
#endif /* m53xxsim_h */

8
arch/m68k/include/asm/m5407sim.h
View File

@ -112,6 +112,7 @@
#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
#define MCFSIM_DMA0ICR MCFSIM_ICR6 /* DMA 0 ICR */
@ -137,10 +138,17 @@
/*
* Define system peripheral IRQ usage.
*/
#define MCF_IRQ_I2C0 29 /* I2C, Level 5 */
#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
#define MCF_IRQ_UART0 73 /* UART0 */
#define MCF_IRQ_UART1 74 /* UART1 */
/*
* I2C module
*/
#define MCFI2C_BASE0 (MCF_MBAR + 0x280)
#define MCFI2C_SIZE0 0x40
/****************************************************************************/
#endif /* m5407sim_h */

11
arch/m68k/include/asm/m54xxsim.h
View File

@ -45,6 +45,7 @@
*/
#define MCF_IRQ_TIMER (MCFINT_VECBASE + 54) /* Slice Timer 0 */
#define MCF_IRQ_PROFILER (MCFINT_VECBASE + 53) /* Slice Timer 1 */
#define MCF_IRQ_I2C0 (MCFINT_VECBASE + 40)
#define MCF_IRQ_UART0 (MCFINT_VECBASE + 35)
#define MCF_IRQ_UART1 (MCFINT_VECBASE + 34)
#define MCF_IRQ_UART2 (MCFINT_VECBASE + 33)
@ -107,4 +108,14 @@
#define MCF_PAR_PSC_RTS_RTS (0x30)
#define MCF_PAR_PSC_CANRX (0x40)
#define MCF_PAR_FECI2CIRQ (MCF_MBAR + 0x00000a44) /* FEC/I2C/IRQ */
#define MCF_PAR_FECI2CIRQ_SDA (1 << 3)
#define MCF_PAR_FECI2CIRQ_SCL (1 << 2)
/*
* I2C module.
*/
#define MCFI2C_BASE0 (MCF_MBAR + 0x8f00)
#define MCFI2C_SIZE0 0x40
#endif /* m54xxsim_h */