ARM i.MX6q: Add GPU, VPU, IPU, and OpenVG resets to System Reset Controller (SRC)
The SRC has auto-deasserting reset bits that control reset lines to the GPU, VPU, IPU, and OpenVG IP modules. This patch adds a reset controller that can be controlled by those devices using the reset controller API. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Documentation/devicetree/bindings/reset/fsl,imx-src.txt
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49
Documentation/devicetree/bindings/reset/fsl,imx-src.txt
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Freescale i.MX System Reset Controller
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======================================
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Please also refer to reset.txt in this directory for common reset
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controller binding usage.
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Required properties:
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- compatible: Should be "fsl,<chip>-src"
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- reg: should be register base and length as documented in the
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datasheet
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- interrupts: Should contain SRC interrupt and CPU WDOG interrupt,
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in this order.
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- #reset-cells: 1, see below
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example:
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src: src@020d8000 {
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compatible = "fsl,imx6q-src";
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reg = <0x020d8000 0x4000>;
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interrupts = <0 91 0x04 0 96 0x04>;
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#reset-cells = <1>;
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};
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Specifying reset lines connected to IP modules
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==============================================
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The system reset controller can be used to reset the GPU, VPU,
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IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
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nodes should specify the reset line on the SRC in their resets
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property, containing a phandle to the SRC device node and a
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RESET_INDEX specifying which module to reset, as described in
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reset.txt
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example:
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ipu1: ipu@02400000 {
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resets = <&src 2>;
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};
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ipu2: ipu@02800000 {
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resets = <&src 4>;
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};
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The following RESET_INDEX values are valid for i.MX5:
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GPU_RESET 0
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VPU_RESET 1
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IPU1_RESET 2
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OPEN_VG_RESET 3
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The following additional RESET_INDEX value is valid for i.MX6:
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IPU2_RESET 4
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@ -76,6 +76,7 @@ config HAVE_IMX_MMDC
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config HAVE_IMX_SRC
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def_bool y if SMP
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select ARCH_HAS_RESET_CONTROLLER
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config IMX_HAVE_IOMUX_V1
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bool
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@ -14,16 +14,72 @@
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/reset-controller.h>
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#include <linux/smp.h>
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#include <asm/smp_plat.h>
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#define SRC_SCR 0x000
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#define SRC_GPR1 0x020
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#define BP_SRC_SCR_WARM_RESET_ENABLE 0
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#define BP_SRC_SCR_SW_GPU_RST 1
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#define BP_SRC_SCR_SW_VPU_RST 2
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#define BP_SRC_SCR_SW_IPU1_RST 3
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#define BP_SRC_SCR_SW_OPEN_VG_RST 4
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#define BP_SRC_SCR_SW_IPU2_RST 12
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#define BP_SRC_SCR_CORE1_RST 14
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#define BP_SRC_SCR_CORE1_ENABLE 22
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static void __iomem *src_base;
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static DEFINE_SPINLOCK(scr_lock);
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static const int sw_reset_bits[5] = {
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BP_SRC_SCR_SW_GPU_RST,
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BP_SRC_SCR_SW_VPU_RST,
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BP_SRC_SCR_SW_IPU1_RST,
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BP_SRC_SCR_SW_OPEN_VG_RST,
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BP_SRC_SCR_SW_IPU2_RST
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};
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static int imx_src_reset_module(struct reset_controller_dev *rcdev,
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unsigned long sw_reset_idx)
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{
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unsigned long timeout;
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unsigned long flags;
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int bit;
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u32 val;
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if (!src_base)
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return -ENODEV;
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if (sw_reset_idx >= ARRAY_SIZE(sw_reset_bits))
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return -EINVAL;
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bit = 1 << sw_reset_bits[sw_reset_idx];
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spin_lock_irqsave(&scr_lock, flags);
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val = readl_relaxed(src_base + SRC_SCR);
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val |= bit;
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock_irqrestore(&scr_lock, flags);
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timeout = jiffies + msecs_to_jiffies(1000);
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while (readl(src_base + SRC_SCR) & bit) {
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if (time_after(jiffies, timeout))
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return -ETIME;
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cpu_relax();
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}
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return 0;
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}
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static struct reset_control_ops imx_src_ops = {
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.reset = imx_src_reset_module,
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};
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static struct reset_controller_dev imx_reset_controller = {
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.ops = &imx_src_ops,
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.nr_resets = ARRAY_SIZE(sw_reset_bits),
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};
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void imx_enable_cpu(int cpu, bool enable)
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{
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@ -31,9 +87,11 @@ void imx_enable_cpu(int cpu, bool enable)
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cpu = cpu_logical_map(cpu);
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mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val = enable ? val | mask : val & ~mask;
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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}
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void imx_set_cpu_jump(int cpu, void *jump_addr)
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@ -60,9 +118,11 @@ void imx_src_prepare_restart(void)
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u32 val;
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/* clear enable bits of secondary cores */
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(0x7 << BP_SRC_SCR_CORE1_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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/* clear persistent entry register of primary core */
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writel_relaxed(0, src_base + SRC_GPR1);
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src_base = of_iomap(np, 0);
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WARN_ON(!src_base);
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imx_reset_controller.of_node = np;
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reset_controller_register(&imx_reset_controller);
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/*
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* force warm reset sources to generate cold reset
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* for a more reliable restart
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*/
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spin_lock(&scr_lock);
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val = readl_relaxed(src_base + SRC_SCR);
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val &= ~(1 << BP_SRC_SCR_WARM_RESET_ENABLE);
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writel_relaxed(val, src_base + SRC_SCR);
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spin_unlock(&scr_lock);
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}
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