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ALSA: ctxfi: Change PLL initialization code

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This is a reworked patch from Creative to change the PLL code to address
unreliable 44100Hz initialization.

Signed-off-by: Harry Butterworth <heb1001@gmail.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Harry Butterworth 2011-06-14 23:09:12 +08:00 committed by Takashi Iwai
parent b3c705aa9e
commit 030aba53ea
1 changed files with 9 additions and 12 deletions
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21
sound/pci/ctxfi/cthw20k2.c
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@ -1316,21 +1316,18 @@ static int hw_pll_init(struct hw *hw, unsigned int rsr)
pllenb = 0xB;
hw_write_20kx(hw, PLL_ENB, pllenb);
pllctl = 0x20D00000;
set_field(&pllctl, PLLCTL_FD, 16 - 4);
hw_write_20kx(hw, PLL_CTL, pllctl);
mdelay(40);
pllctl = hw_read_20kx(hw, PLL_CTL);
pllctl = 0x20C00000;
set_field(&pllctl, PLLCTL_B, 0);
if (48000 == rsr) {
set_field(&pllctl, PLLCTL_FD, 16 - 2);
set_field(&pllctl, PLLCTL_RD, 1 - 1); /* 3000*16/1 = 48000 */
} else { /* 44100 */
set_field(&pllctl, PLLCTL_FD, 147 - 2);
set_field(&pllctl, PLLCTL_RD, 10 - 1); /* 3000*147/10 = 44100 */
}
set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
hw_write_20kx(hw, PLL_CTL, pllctl);
mdelay(40);
pllctl = hw_read_20kx(hw, PLL_CTL);
set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
hw_write_20kx(hw, PLL_CTL, pllctl);
mdelay(40);
for (i = 0; i < 1000; i++) {
pllstat = hw_read_20kx(hw, PLL_STAT);
if (get_field(pllstat, PLLSTAT_PD))