i7core_edac: convert driver to use the new edac ABI
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
parent
70e2a8379b
commit
0975c16f4f
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@ -257,7 +257,6 @@ struct i7core_pvt {
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struct i7core_channel channel[NUM_CHANS];
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int ce_count_available;
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int csrow_map[NUM_CHANS][MAX_DIMMS];
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/* ECC corrected errors counts per udimm */
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unsigned long udimm_ce_count[MAX_DIMMS];
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@ -492,113 +491,12 @@ static void free_i7core_dev(struct i7core_dev *i7core_dev)
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/****************************************************************************
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Memory check routines
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****************************************************************************/
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static struct pci_dev *get_pdev_slot_func(u8 socket, unsigned slot,
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unsigned func)
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{
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struct i7core_dev *i7core_dev = get_i7core_dev(socket);
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int i;
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if (!i7core_dev)
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return NULL;
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for (i = 0; i < i7core_dev->n_devs; i++) {
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if (!i7core_dev->pdev[i])
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continue;
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if (PCI_SLOT(i7core_dev->pdev[i]->devfn) == slot &&
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PCI_FUNC(i7core_dev->pdev[i]->devfn) == func) {
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return i7core_dev->pdev[i];
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}
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}
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return NULL;
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}
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/**
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* i7core_get_active_channels() - gets the number of channels and csrows
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* @socket: Quick Path Interconnect socket
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* @channels: Number of channels that will be returned
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* @csrows: Number of csrows found
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*
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* Since EDAC core needs to know in advance the number of available channels
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* and csrows, in order to allocate memory for csrows/channels, it is needed
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* to run two similar steps. At the first step, implemented on this function,
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* it checks the number of csrows/channels present at one socket.
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* this is used in order to properly allocate the size of mci components.
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*
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* It should be noticed that none of the current available datasheets explain
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* or even mention how csrows are seen by the memory controller. So, we need
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* to add a fake description for csrows.
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* So, this driver is attributing one DIMM memory for one csrow.
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*/
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static int i7core_get_active_channels(const u8 socket, unsigned *channels,
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unsigned *csrows)
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{
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struct pci_dev *pdev = NULL;
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int i, j;
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u32 status, control;
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*channels = 0;
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*csrows = 0;
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pdev = get_pdev_slot_func(socket, 3, 0);
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if (!pdev) {
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i7core_printk(KERN_ERR, "Couldn't find socket %d fn 3.0!!!\n",
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socket);
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return -ENODEV;
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}
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/* Device 3 function 0 reads */
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pci_read_config_dword(pdev, MC_STATUS, &status);
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pci_read_config_dword(pdev, MC_CONTROL, &control);
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for (i = 0; i < NUM_CHANS; i++) {
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u32 dimm_dod[3];
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/* Check if the channel is active */
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if (!(control & (1 << (8 + i))))
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continue;
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/* Check if the channel is disabled */
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if (status & (1 << i))
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continue;
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pdev = get_pdev_slot_func(socket, i + 4, 1);
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if (!pdev) {
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i7core_printk(KERN_ERR, "Couldn't find socket %d "
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"fn %d.%d!!!\n",
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socket, i + 4, 1);
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return -ENODEV;
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}
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/* Devices 4-6 function 1 */
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pci_read_config_dword(pdev,
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MC_DOD_CH_DIMM0, &dimm_dod[0]);
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pci_read_config_dword(pdev,
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MC_DOD_CH_DIMM1, &dimm_dod[1]);
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pci_read_config_dword(pdev,
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MC_DOD_CH_DIMM2, &dimm_dod[2]);
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(*channels)++;
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for (j = 0; j < 3; j++) {
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if (!DIMM_PRESENT(dimm_dod[j]))
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continue;
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(*csrows)++;
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}
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}
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debugf0("Number of active channels on socket %d: %d\n",
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socket, *channels);
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return 0;
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}
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static int get_dimm_config(struct mem_ctl_info *mci)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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struct csrow_info *csr;
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struct pci_dev *pdev;
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int i, j;
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int csrow = 0;
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enum edac_type mode;
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enum mem_type mtype;
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struct dimm_info *dimm;
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@ -696,6 +594,8 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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if (!DIMM_PRESENT(dimm_dod[j]))
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continue;
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dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
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i, j, 0);
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banks = numbank(MC_DOD_NUMBANK(dimm_dod[j]));
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ranks = numrank(MC_DOD_NUMRANK(dimm_dod[j]));
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rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
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@ -704,8 +604,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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/* DDR3 has 8 I/O banks */
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size = (rows * cols * banks * ranks) >> (20 - 3);
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pvt->channel[i].dimms++;
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debugf0("\tdimm %d %d Mb offset: %x, "
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"bank: %d, rank: %d, row: %#x, col: %#x\n",
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j, size,
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@ -714,11 +612,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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npages = MiB_TO_PAGES(size);
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csr = &mci->csrows[csrow];
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pvt->csrow_map[i][j] = csrow;
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dimm = csr->channels[0].dimm;
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dimm->nr_pages = npages;
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switch (banks) {
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@ -741,7 +634,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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dimm->grain = 8;
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dimm->edac_mode = mode;
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dimm->mtype = mtype;
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csrow++;
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}
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pci_read_config_dword(pdev, MC_SAG_CH_0, &value[0]);
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@ -1557,22 +1449,16 @@ static int mci_bind_devs(struct mem_ctl_info *mci,
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/****************************************************************************
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Error check routines
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****************************************************************************/
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static void i7core_rdimm_update_csrow(struct mem_ctl_info *mci,
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static void i7core_rdimm_update_errcount(struct mem_ctl_info *mci,
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const int chan,
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const int dimm,
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const int add)
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{
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char *msg;
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struct i7core_pvt *pvt = mci->pvt_info;
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int row = pvt->csrow_map[chan][dimm], i;
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int i;
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for (i = 0; i < add; i++) {
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msg = kasprintf(GFP_KERNEL, "Corrected error "
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"(Socket=%d channel=%d dimm=%d)",
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pvt->i7core_dev->socket, chan, dimm);
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edac_mc_handle_fbd_ce(mci, row, 0, msg);
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kfree (msg);
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
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chan, dimm, -1, "error", "", NULL);
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}
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}
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@ -1613,11 +1499,11 @@ static void i7core_rdimm_update_ce_count(struct mem_ctl_info *mci,
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/*updated the edac core */
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if (add0 != 0)
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i7core_rdimm_update_csrow(mci, chan, 0, add0);
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i7core_rdimm_update_errcount(mci, chan, 0, add0);
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if (add1 != 0)
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i7core_rdimm_update_csrow(mci, chan, 1, add1);
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i7core_rdimm_update_errcount(mci, chan, 1, add1);
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if (add2 != 0)
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i7core_rdimm_update_csrow(mci, chan, 2, add2);
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i7core_rdimm_update_errcount(mci, chan, 2, add2);
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}
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@ -1738,19 +1624,29 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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char *type, *optype, *err, *msg;
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enum hw_event_mc_err_type tp_event;
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unsigned long error = m->status & 0x1ff0000l;
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bool uncorrected_error = m->mcgstatus & 1ll << 61;
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bool ripv = m->mcgstatus & 1;
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u32 optypenum = (m->status >> 4) & 0x07;
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u32 core_err_cnt = (m->status >> 38) & 0x7fff;
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u32 dimm = (m->misc >> 16) & 0x3;
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u32 channel = (m->misc >> 18) & 0x3;
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u32 syndrome = m->misc >> 32;
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u32 errnum = find_first_bit(&error, 32);
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int csrow;
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if (m->mcgstatus & 1)
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type = "FATAL";
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else
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type = "NON_FATAL";
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if (uncorrected_error) {
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if (ripv) {
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type = "FATAL";
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tp_event = HW_EVENT_ERR_FATAL;
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} else {
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type = "NON_FATAL";
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tp_event = HW_EVENT_ERR_UNCORRECTED;
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}
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} else {
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type = "CORRECTED";
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tp_event = HW_EVENT_ERR_CORRECTED;
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}
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switch (optypenum) {
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case 0:
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@ -1805,25 +1701,23 @@ static void i7core_mce_output_error(struct mem_ctl_info *mci,
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err = "unknown";
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}
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/* FIXME: should convert addr into bank and rank information */
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msg = kasprintf(GFP_ATOMIC,
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"%s (addr = 0x%08llx, cpu=%d, Dimm=%d, Channel=%d, "
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"syndrome=0x%08x, count=%d, Err=%08llx:%08llx (%s: %s))\n",
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type, (long long) m->addr, m->cpu, dimm, channel,
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syndrome, core_err_cnt, (long long)m->status,
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(long long)m->misc, optype, err);
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"addr=0x%08llx cpu=%d count=%d Err=%08llx:%08llx (%s: %s))\n",
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(long long) m->addr, m->cpu, core_err_cnt,
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(long long)m->status, (long long)m->misc, optype, err);
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debugf0("%s", msg);
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csrow = pvt->csrow_map[channel][dimm];
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/* Call the helper to output message */
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if (m->mcgstatus & 1)
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edac_mc_handle_fbd_ue(mci, csrow, 0,
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0 /* FIXME: should be channel here */, msg);
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else if (!pvt->is_registered)
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edac_mc_handle_fbd_ce(mci, csrow,
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0 /* FIXME: should be channel here */, msg);
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/*
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* Call the helper to output message
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* FIXME: what to do if core_err_cnt > 1? Currently, it generates
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* only one event
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*/
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if (uncorrected_error || !pvt->is_registered)
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edac_mc_handle_error(tp_event, mci,
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m->addr >> PAGE_SHIFT,
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m->addr & ~PAGE_MASK,
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syndrome,
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channel, dimm, -1,
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err, msg, m);
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kfree(msg);
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}
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@ -2242,15 +2136,19 @@ static int i7core_register_mci(struct i7core_dev *i7core_dev)
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{
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struct mem_ctl_info *mci;
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struct i7core_pvt *pvt;
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int rc, channels, csrows;
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/* Check the number of active and not disabled channels */
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rc = i7core_get_active_channels(i7core_dev->socket, &channels, &csrows);
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if (unlikely(rc < 0))
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return rc;
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int rc;
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struct edac_mc_layer layers[2];
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/* allocate a new MC control structure */
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mci = edac_mc_alloc(sizeof(*pvt), csrows, channels, i7core_dev->socket);
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layers[0].type = EDAC_MC_LAYER_CHANNEL;
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layers[0].size = NUM_CHANS;
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layers[0].is_virt_csrow = false;
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layers[1].type = EDAC_MC_LAYER_SLOT;
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layers[1].size = MAX_DIMMS;
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layers[1].is_virt_csrow = true;
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mci = new_edac_mc_alloc(i7core_dev->socket, ARRAY_SIZE(layers), layers,
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sizeof(*pvt));
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if (unlikely(!mci))
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return -ENOMEM;
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