ide: remove the sgiioc4 driver
The SGI SN2 support is about to be removed. Remove this driver that depends on the SN2 support. Signed-off-by: Christoph Hellwig <hch@lst.de> Link: https://lkml.kernel.org/r/20190813072514.23299-5-hch@lst.de Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
parent
defdeacb1b
commit
0b43ba0dbe
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@ -51,7 +51,6 @@ CONFIG_BLK_DEV_IDECD=y
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CONFIG_BLK_DEV_GENERIC=y
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CONFIG_BLK_DEV_CMD64X=y
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CONFIG_BLK_DEV_PIIX=y
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CONFIG_BLK_DEV_SGIIOC4=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_CHR_DEV_ST=m
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CONFIG_BLK_DEV_SR=m
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@ -44,7 +44,6 @@ CONFIG_IDE_GENERIC=y
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CONFIG_BLK_DEV_GENERIC=y
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CONFIG_BLK_DEV_CMD64X=y
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CONFIG_BLK_DEV_PIIX=y
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CONFIG_BLK_DEV_SGIIOC4=y
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_CHR_DEV_ST=m
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@ -30,8 +30,6 @@ source "drivers/block/Kconfig"
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source "drivers/nvme/Kconfig"
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# misc before ide - BLK_DEV_SGIIOC4 depends on SGI_IOC4
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source "drivers/misc/Kconfig"
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source "drivers/ide/Kconfig"
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@ -567,15 +567,6 @@ config BLK_DEV_SVWKS
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This driver adds PIO/(U)DMA support for the ServerWorks OSB4/CSB5
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chipsets.
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config BLK_DEV_SGIIOC4
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tristate "Silicon Graphics IOC4 chipset ATA/ATAPI support"
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depends on (IA64_SGI_SN2 || IA64_GENERIC) && SGI_IOC4
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select BLK_DEV_IDEDMA_PCI
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help
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This driver adds PIO & MultiMode DMA-2 support for the SGI IOC4
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chipset, which has one channel and can support two devices.
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Please say Y here if you have an Altix System from SGI.
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config BLK_DEV_SIIMAGE
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tristate "Silicon Image chipset support"
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select BLK_DEV_IDEDMA_PCI
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@ -59,7 +59,6 @@ obj-$(CONFIG_BLK_DEV_PDC202XX_NEW) += pdc202xx_new.o
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obj-$(CONFIG_BLK_DEV_PIIX) += piix.o
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obj-$(CONFIG_BLK_DEV_RZ1000) += rz1000.o
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obj-$(CONFIG_BLK_DEV_SVWKS) += serverworks.o
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obj-$(CONFIG_BLK_DEV_SGIIOC4) += sgiioc4.o
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obj-$(CONFIG_BLK_DEV_SIIMAGE) += siimage.o
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obj-$(CONFIG_BLK_DEV_SIS5513) += sis5513.o
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obj-$(CONFIG_BLK_DEV_SL82C105) += sl82c105.o
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@ -1,630 +0,0 @@
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/*
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* Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
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* Copyright (C) 2008-2009 MontaVista Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* For further information regarding this notice, see:
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*
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* http://oss.sgi.com/projects/GenInfo/NoticeExplan
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/blkdev.h>
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#include <linux/scatterlist.h>
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#include <linux/ioc4.h>
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#include <linux/io.h>
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#include <linux/ide.h>
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#define DRV_NAME "SGIIOC4"
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/* IOC4 Specific Definitions */
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#define IOC4_CMD_OFFSET 0x100
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#define IOC4_CTRL_OFFSET 0x120
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#define IOC4_DMA_OFFSET 0x140
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#define IOC4_INTR_OFFSET 0x0
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#define IOC4_TIMING 0x00
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#define IOC4_DMA_PTR_L 0x01
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#define IOC4_DMA_PTR_H 0x02
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#define IOC4_DMA_ADDR_L 0x03
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#define IOC4_DMA_ADDR_H 0x04
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#define IOC4_BC_DEV 0x05
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#define IOC4_BC_MEM 0x06
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#define IOC4_DMA_CTRL 0x07
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#define IOC4_DMA_END_ADDR 0x08
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/* Bits in the IOC4 Control/Status Register */
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#define IOC4_S_DMA_START 0x01
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#define IOC4_S_DMA_STOP 0x02
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#define IOC4_S_DMA_DIR 0x04
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#define IOC4_S_DMA_ACTIVE 0x08
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#define IOC4_S_DMA_ERROR 0x10
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#define IOC4_ATA_MEMERR 0x02
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/* Read/Write Directions */
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#define IOC4_DMA_WRITE 0x04
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#define IOC4_DMA_READ 0x00
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/* Interrupt Register Offsets */
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#define IOC4_INTR_REG 0x03
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#define IOC4_INTR_SET 0x05
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#define IOC4_INTR_CLEAR 0x07
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#define IOC4_IDE_CACHELINE_SIZE 128
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#define IOC4_CMD_CTL_BLK_SIZE 0x20
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#define IOC4_SUPPORTED_FIRMWARE_REV 46
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struct ioc4_dma_regs {
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u32 timing_reg0;
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u32 timing_reg1;
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u32 low_mem_ptr;
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u32 high_mem_ptr;
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u32 low_mem_addr;
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u32 high_mem_addr;
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u32 dev_byte_count;
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u32 mem_byte_count;
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u32 status;
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};
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/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
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/* IOC4 has only 1 IDE channel */
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#define IOC4_PRD_BYTES 16
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#define IOC4_PRD_ENTRIES (PAGE_SIZE / (4 * IOC4_PRD_BYTES))
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static void sgiioc4_init_hwif_ports(struct ide_hw *hw,
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unsigned long data_port,
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unsigned long ctrl_port,
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unsigned long irq_port)
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{
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unsigned long reg = data_port;
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int i;
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/* Registers are word (32 bit) aligned */
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for (i = 0; i <= 7; i++)
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hw->io_ports_array[i] = reg + i * 4;
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hw->io_ports.ctl_addr = ctrl_port;
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hw->io_ports.irq_addr = irq_port;
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}
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static int sgiioc4_checkirq(ide_hwif_t *hwif)
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{
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unsigned long intr_addr = hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
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if (readl((void __iomem *)intr_addr) & 0x03)
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return 1;
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return 0;
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}
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static u8 sgiioc4_read_status(ide_hwif_t *);
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static int sgiioc4_clearirq(ide_drive_t *drive)
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{
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u32 intr_reg;
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ide_hwif_t *hwif = drive->hwif;
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struct ide_io_ports *io_ports = &hwif->io_ports;
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unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
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/* Code to check for PCI error conditions */
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intr_reg = readl((void __iomem *)other_ir);
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if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
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/*
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* Using sgiioc4_read_status to read the Status register has a
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* side effect of clearing the interrupt. The first read should
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* clear it if it is set. The second read should return
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* a "clear" status if it got cleared. If not, then spin
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* for a bit trying to clear it.
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*/
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u8 stat = sgiioc4_read_status(hwif);
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int count = 0;
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stat = sgiioc4_read_status(hwif);
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while ((stat & ATA_BUSY) && (count++ < 100)) {
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udelay(1);
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stat = sgiioc4_read_status(hwif);
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}
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if (intr_reg & 0x02) {
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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/* Error when transferring DMA data on PCI bus */
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u32 pci_err_addr_low, pci_err_addr_high,
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pci_stat_cmd_reg;
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pci_err_addr_low =
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readl((void __iomem *)io_ports->irq_addr);
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pci_err_addr_high =
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readl((void __iomem *)(io_ports->irq_addr + 4));
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pci_read_config_dword(dev, PCI_COMMAND,
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&pci_stat_cmd_reg);
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printk(KERN_ERR "%s(%s): PCI Bus Error when doing DMA: "
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"status-cmd reg is 0x%x\n",
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__func__, drive->name, pci_stat_cmd_reg);
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printk(KERN_ERR "%s(%s): PCI Error Address is 0x%x%x\n",
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__func__, drive->name,
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pci_err_addr_high, pci_err_addr_low);
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/* Clear the PCI Error indicator */
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pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
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}
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/* Clear the Interrupt, Error bits on the IOC4 */
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writel(0x03, (void __iomem *)other_ir);
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intr_reg = readl((void __iomem *)other_ir);
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}
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return intr_reg & 3;
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}
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static void sgiioc4_dma_start(ide_drive_t *drive)
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{
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ide_hwif_t *hwif = drive->hwif;
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unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
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unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
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unsigned int temp_reg = reg | IOC4_S_DMA_START;
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writel(temp_reg, (void __iomem *)ioc4_dma_addr);
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}
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static u32 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
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{
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unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
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u32 ioc4_dma;
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int count;
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count = 0;
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ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
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while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
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udelay(1);
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ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
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}
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return ioc4_dma;
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}
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/* Stops the IOC4 DMA Engine */
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static int sgiioc4_dma_end(ide_drive_t *drive)
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{
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u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
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ide_hwif_t *hwif = drive->hwif;
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unsigned long dma_base = hwif->dma_base;
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int dma_stat = 0;
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unsigned long *ending_dma = ide_get_hwifdata(hwif);
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writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
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ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
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if (ioc4_dma & IOC4_S_DMA_STOP) {
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printk(KERN_ERR
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"%s(%s): IOC4 DMA STOP bit is still 1 :"
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"ioc4_dma_reg 0x%x\n",
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__func__, drive->name, ioc4_dma);
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dma_stat = 1;
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}
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/*
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* The IOC4 will DMA 1's to the ending DMA area to indicate that
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* previous data DMA is complete. This is necessary because of relaxed
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* ordering between register reads and DMA writes on the Altix.
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*/
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while ((cnt++ < 200) && (!valid)) {
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for (num = 0; num < 16; num++) {
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if (ending_dma[num]) {
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valid = 1;
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break;
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}
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}
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udelay(1);
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}
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if (!valid) {
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printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
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drive->name);
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dma_stat = 1;
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}
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bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
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bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
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if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
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if (bc_dev > bc_mem + 8) {
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printk(KERN_ERR
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"%s(%s): WARNING!! byte_count_dev %d "
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"!= byte_count_mem %d\n",
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__func__, drive->name, bc_dev, bc_mem);
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}
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}
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return dma_stat;
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}
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static void sgiioc4_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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}
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/* Returns 1 if DMA IRQ issued, 0 otherwise */
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static int sgiioc4_dma_test_irq(ide_drive_t *drive)
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{
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return sgiioc4_checkirq(drive->hwif);
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}
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static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
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{
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if (!on)
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sgiioc4_clearirq(drive);
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}
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static void sgiioc4_resetproc(ide_drive_t *drive)
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{
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struct ide_cmd *cmd = &drive->hwif->cmd;
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sgiioc4_dma_end(drive);
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ide_dma_unmap_sg(drive, cmd);
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sgiioc4_clearirq(drive);
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}
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static void sgiioc4_dma_lost_irq(ide_drive_t *drive)
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{
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sgiioc4_resetproc(drive);
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ide_dma_lost_irq(drive);
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}
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static u8 sgiioc4_read_status(ide_hwif_t *hwif)
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{
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unsigned long port = hwif->io_ports.status_addr;
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u8 reg = (u8) readb((void __iomem *) port);
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if (!(reg & ATA_BUSY)) { /* Not busy... check for interrupt */
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unsigned long other_ir = port - 0x110;
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unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
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/* Clear the Interrupt, Error bits on the IOC4 */
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if (intr_reg & 0x03) {
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writel(0x03, (void __iomem *) other_ir);
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intr_reg = (u32) readl((void __iomem *) other_ir);
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}
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}
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return reg;
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}
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/* Creates a DMA map for the scatter-gather list entries */
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static int ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
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int num_ports = sizeof(struct ioc4_dma_regs);
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void *pad;
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printk(KERN_INFO " %s: MMIO-DMA\n", hwif->name);
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if (request_mem_region(dma_base, num_ports, hwif->name) == NULL) {
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printk(KERN_ERR "%s(%s) -- ERROR: addresses 0x%08lx to 0x%08lx "
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"already in use\n", __func__, hwif->name,
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dma_base, dma_base + num_ports - 1);
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return -1;
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}
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hwif->dma_base = (unsigned long)hwif->io_ports.irq_addr +
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IOC4_DMA_OFFSET;
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hwif->sg_max_nents = IOC4_PRD_ENTRIES;
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hwif->prd_max_nents = IOC4_PRD_ENTRIES;
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hwif->prd_ent_size = IOC4_PRD_BYTES;
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if (ide_allocate_dma_engine(hwif))
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goto dma_pci_alloc_failure;
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pad = dma_alloc_coherent(&dev->dev, IOC4_IDE_CACHELINE_SIZE,
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(dma_addr_t *)&hwif->extra_base, GFP_KERNEL);
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if (pad) {
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ide_set_hwifdata(hwif, pad);
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return 0;
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}
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ide_release_dma_engine(hwif);
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printk(KERN_ERR "%s(%s) -- ERROR: Unable to allocate DMA maps\n",
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__func__, hwif->name);
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printk(KERN_INFO "%s: changing from DMA to PIO mode", hwif->name);
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dma_pci_alloc_failure:
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release_mem_region(dma_base, num_ports);
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return -1;
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}
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/* Initializes the IOC4 DMA Engine */
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static void sgiioc4_configure_for_dma(int dma_direction, ide_drive_t *drive)
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{
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u32 ioc4_dma;
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ide_hwif_t *hwif = drive->hwif;
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unsigned long dma_base = hwif->dma_base;
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unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
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u32 dma_addr, ending_dma_addr;
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ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
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if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
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printk(KERN_WARNING "%s(%s): Warning!! DMA from previous "
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"transfer was still active\n", __func__, drive->name);
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writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
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ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
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if (ioc4_dma & IOC4_S_DMA_STOP)
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printk(KERN_ERR "%s(%s): IOC4 DMA STOP bit is "
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"still 1\n", __func__, drive->name);
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}
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|
||||
ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
|
||||
if (ioc4_dma & IOC4_S_DMA_ERROR) {
|
||||
printk(KERN_WARNING "%s(%s): Warning!! DMA Error during "
|
||||
"previous transfer, status 0x%x\n",
|
||||
__func__, drive->name, ioc4_dma);
|
||||
writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
|
||||
ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
|
||||
|
||||
if (ioc4_dma & IOC4_S_DMA_STOP)
|
||||
printk(KERN_ERR "%s(%s): IOC4 DMA STOP bit is "
|
||||
"still 1\n", __func__, drive->name);
|
||||
}
|
||||
|
||||
/* Address of the Scatter Gather List */
|
||||
dma_addr = cpu_to_le32(hwif->dmatable_dma);
|
||||
writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
|
||||
|
||||
/* Address of the Ending DMA */
|
||||
memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
|
||||
ending_dma_addr = cpu_to_le32(hwif->extra_base);
|
||||
writel(ending_dma_addr, (void __iomem *)(dma_base +
|
||||
IOC4_DMA_END_ADDR * 4));
|
||||
|
||||
writel(dma_direction, (void __iomem *)ioc4_dma_addr);
|
||||
}
|
||||
|
||||
/* IOC4 Scatter Gather list Format */
|
||||
/* 128 Bit entries to support 64 bit addresses in the future */
|
||||
/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
|
||||
/* --------------------------------------------------------------------- */
|
||||
/* | Upper 32 bits - Zero | Lower 32 bits- address | */
|
||||
/* --------------------------------------------------------------------- */
|
||||
/* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
|
||||
/* --------------------------------------------------------------------- */
|
||||
/* Creates the scatter gather list, DMA Table */
|
||||
|
||||
static int sgiioc4_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
|
||||
{
|
||||
ide_hwif_t *hwif = drive->hwif;
|
||||
unsigned int *table = hwif->dmatable_cpu;
|
||||
unsigned int count = 0, i = cmd->sg_nents;
|
||||
struct scatterlist *sg = hwif->sg_table;
|
||||
|
||||
while (i && sg_dma_len(sg)) {
|
||||
dma_addr_t cur_addr;
|
||||
int cur_len;
|
||||
cur_addr = sg_dma_address(sg);
|
||||
cur_len = sg_dma_len(sg);
|
||||
|
||||
while (cur_len) {
|
||||
if (count++ >= IOC4_PRD_ENTRIES) {
|
||||
printk(KERN_WARNING
|
||||
"%s: DMA table too small\n",
|
||||
drive->name);
|
||||
return 0;
|
||||
} else {
|
||||
u32 bcount =
|
||||
0x10000 - (cur_addr & 0xffff);
|
||||
|
||||
if (bcount > cur_len)
|
||||
bcount = cur_len;
|
||||
|
||||
/*
|
||||
* Put the address, length in
|
||||
* the IOC4 dma-table format
|
||||
*/
|
||||
*table = 0x0;
|
||||
table++;
|
||||
*table = cpu_to_be32(cur_addr);
|
||||
table++;
|
||||
*table = 0x0;
|
||||
table++;
|
||||
|
||||
*table = cpu_to_be32(bcount);
|
||||
table++;
|
||||
|
||||
cur_addr += bcount;
|
||||
cur_len -= bcount;
|
||||
}
|
||||
}
|
||||
|
||||
sg = sg_next(sg);
|
||||
i--;
|
||||
}
|
||||
|
||||
if (count) {
|
||||
table--;
|
||||
*table |= cpu_to_be32(0x80000000);
|
||||
return count;
|
||||
}
|
||||
|
||||
return 0; /* revert to PIO for this request */
|
||||
}
|
||||
|
||||
static int sgiioc4_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
|
||||
{
|
||||
int ddir;
|
||||
u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
|
||||
|
||||
if (sgiioc4_build_dmatable(drive, cmd) == 0)
|
||||
/* try PIO instead of DMA */
|
||||
return 1;
|
||||
|
||||
if (write)
|
||||
/* Writes TO the IOC4 FROM Main Memory */
|
||||
ddir = IOC4_DMA_READ;
|
||||
else
|
||||
/* Writes FROM the IOC4 TO Main Memory */
|
||||
ddir = IOC4_DMA_WRITE;
|
||||
|
||||
sgiioc4_configure_for_dma(ddir, drive);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct ide_tp_ops sgiioc4_tp_ops = {
|
||||
.exec_command = ide_exec_command,
|
||||
.read_status = sgiioc4_read_status,
|
||||
.read_altstatus = ide_read_altstatus,
|
||||
.write_devctl = ide_write_devctl,
|
||||
|
||||
.dev_select = ide_dev_select,
|
||||
.tf_load = ide_tf_load,
|
||||
.tf_read = ide_tf_read,
|
||||
|
||||
.input_data = ide_input_data,
|
||||
.output_data = ide_output_data,
|
||||
};
|
||||
|
||||
static const struct ide_port_ops sgiioc4_port_ops = {
|
||||
.set_dma_mode = sgiioc4_set_dma_mode,
|
||||
/* reset DMA engine, clear IRQs */
|
||||
.resetproc = sgiioc4_resetproc,
|
||||
};
|
||||
|
||||
static const struct ide_dma_ops sgiioc4_dma_ops = {
|
||||
.dma_host_set = sgiioc4_dma_host_set,
|
||||
.dma_setup = sgiioc4_dma_setup,
|
||||
.dma_start = sgiioc4_dma_start,
|
||||
.dma_end = sgiioc4_dma_end,
|
||||
.dma_test_irq = sgiioc4_dma_test_irq,
|
||||
.dma_lost_irq = sgiioc4_dma_lost_irq,
|
||||
};
|
||||
|
||||
static const struct ide_port_info sgiioc4_port_info = {
|
||||
.name = DRV_NAME,
|
||||
.chipset = ide_pci,
|
||||
.init_dma = ide_dma_sgiioc4,
|
||||
.tp_ops = &sgiioc4_tp_ops,
|
||||
.port_ops = &sgiioc4_port_ops,
|
||||
.dma_ops = &sgiioc4_dma_ops,
|
||||
.host_flags = IDE_HFLAG_MMIO,
|
||||
.irq_flags = IRQF_SHARED,
|
||||
.mwdma_mask = ATA_MWDMA2_ONLY,
|
||||
};
|
||||
|
||||
static int sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
|
||||
{
|
||||
unsigned long cmd_base, irqport;
|
||||
unsigned long bar0, cmd_phys_base, ctl;
|
||||
void __iomem *virt_base;
|
||||
struct ide_hw hw, *hws[] = { &hw };
|
||||
int rc;
|
||||
|
||||
/* Get the CmdBlk and CtrlBlk base registers */
|
||||
bar0 = pci_resource_start(dev, 0);
|
||||
virt_base = pci_ioremap_bar(dev, 0);
|
||||
if (virt_base == NULL) {
|
||||
printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
|
||||
DRV_NAME, bar0);
|
||||
return -ENOMEM;
|
||||
}
|
||||
cmd_base = (unsigned long)virt_base + IOC4_CMD_OFFSET;
|
||||
ctl = (unsigned long)virt_base + IOC4_CTRL_OFFSET;
|
||||
irqport = (unsigned long)virt_base + IOC4_INTR_OFFSET;
|
||||
|
||||
cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
|
||||
if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
|
||||
DRV_NAME) == NULL) {
|
||||
printk(KERN_ERR "%s %s -- ERROR: addresses 0x%08lx to 0x%08lx "
|
||||
"already in use\n", DRV_NAME, pci_name(dev),
|
||||
cmd_phys_base, cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
|
||||
rc = -EBUSY;
|
||||
goto req_mem_rgn_err;
|
||||
}
|
||||
|
||||
/* Initialize the IO registers */
|
||||
memset(&hw, 0, sizeof(hw));
|
||||
sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
|
||||
hw.irq = dev->irq;
|
||||
hw.dev = &dev->dev;
|
||||
|
||||
/* Initialize chipset IRQ registers */
|
||||
writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
|
||||
|
||||
rc = ide_host_add(&sgiioc4_port_info, hws, 1, NULL);
|
||||
if (!rc)
|
||||
return 0;
|
||||
|
||||
release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
|
||||
req_mem_rgn_err:
|
||||
iounmap(virt_base);
|
||||
return rc;
|
||||
}
|
||||
|
||||
static unsigned int pci_init_sgiioc4(struct pci_dev *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
|
||||
DRV_NAME, pci_name(dev), dev->revision);
|
||||
|
||||
if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
|
||||
printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
|
||||
"firmware is obsolete - please upgrade to "
|
||||
"revision46 or higher\n",
|
||||
DRV_NAME, pci_name(dev));
|
||||
ret = -EAGAIN;
|
||||
goto out;
|
||||
}
|
||||
ret = sgiioc4_ide_setup_pci_device(dev);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ioc4_ide_attach_one(struct ioc4_driver_data *idd)
|
||||
{
|
||||
/*
|
||||
* PCI-RT does not bring out IDE connection.
|
||||
* Do not attach to this particular IOC4.
|
||||
*/
|
||||
if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
|
||||
return 0;
|
||||
|
||||
return pci_init_sgiioc4(idd->idd_pdev);
|
||||
}
|
||||
|
||||
static struct ioc4_submodule ioc4_ide_submodule = {
|
||||
.is_name = "IOC4_ide",
|
||||
.is_owner = THIS_MODULE,
|
||||
.is_probe = ioc4_ide_attach_one,
|
||||
};
|
||||
|
||||
static int __init ioc4_ide_init(void)
|
||||
{
|
||||
return ioc4_register_submodule(&ioc4_ide_submodule);
|
||||
}
|
||||
|
||||
late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
|
||||
|
||||
MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
|
||||
MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
|
||||
MODULE_LICENSE("GPL");
|
Loading…
Reference in New Issue
Block a user