[WATCHDOG] iTCO_wdt: fix SMI_EN regression 2
bugzilla: #12363
commit 7cd5b08be3
added a second regression:
some Dell's and Compaq's lockup on boot. So we revert most of the code.
The ICH9 reboot issue remains in place and will need some more fixing... :-(
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
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@ -406,7 +406,7 @@ config ITCO_WDT
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---help---
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Hardware driver for the intel TCO timer based watchdog devices.
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These drivers are included in the Intel 82801 I/O Controller
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Hub family (from ICH0 up to ICH8) and in the Intel 6300ESB
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Hub family (from ICH0 up to ICH10) and in the Intel 63xxESB
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controller hub.
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The TCO (Total Cost of Ownership) timer is a watchdog timer
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@ -1,7 +1,7 @@
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/*
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* intel TCO vendor specific watchdog driver support
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*
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* (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>.
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* (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -19,7 +19,7 @@
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/* Module and version information */
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#define DRV_NAME "iTCO_vendor_support"
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#define DRV_VERSION "1.02"
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#define DRV_VERSION "1.03"
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#define PFX DRV_NAME ": "
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/* Includes */
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@ -77,6 +77,26 @@ MODULE_PARM_DESC(vendorsupport, "iTCO vendor specific support mode, default=0 (n
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* 20.6 seconds.
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*/
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static void supermicro_old_pre_start(unsigned long acpibase)
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{
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unsigned long val32;
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/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
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val32 = inl(SMI_EN);
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val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
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outl(val32, SMI_EN); /* Needed to activate watchdog */
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}
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static void supermicro_old_pre_stop(unsigned long acpibase)
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{
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unsigned long val32;
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/* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
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val32 = inl(SMI_EN);
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val32 |= 0x00002000; /* Turn on SMI clearing watchdog */
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outl(val32, SMI_EN); /* Needed to deactivate watchdog */
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}
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static void supermicro_old_pre_keepalive(unsigned long acpibase)
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{
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/* Reload TCO Timer (done in iTCO_wdt_keepalive) + */
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@ -228,14 +248,18 @@ static void supermicro_new_pre_set_heartbeat(unsigned int heartbeat)
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void iTCO_vendor_pre_start(unsigned long acpibase,
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unsigned int heartbeat)
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{
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if (vendorsupport == SUPERMICRO_NEW_BOARD)
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if (vendorsupport == SUPERMICRO_OLD_BOARD)
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supermicro_old_pre_start(acpibase);
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else if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_start(heartbeat);
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_start);
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void iTCO_vendor_pre_stop(unsigned long acpibase)
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{
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if (vendorsupport == SUPERMICRO_NEW_BOARD)
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if (vendorsupport == SUPERMICRO_OLD_BOARD)
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supermicro_old_pre_stop(acpibase);
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else if (vendorsupport == SUPERMICRO_NEW_BOARD)
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supermicro_new_pre_stop();
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}
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EXPORT_SYMBOL(iTCO_vendor_pre_stop);
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@ -1,7 +1,7 @@
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/*
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* intel TCO Watchdog Driver (Used in i82801 and i6300ESB chipsets)
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* intel TCO Watchdog Driver (Used in i82801 and i63xxESB chipsets)
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*
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* (c) Copyright 2006-2008 Wim Van Sebroeck <wim@iguana.be>.
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* (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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@ -63,7 +63,7 @@
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/* Module and version information */
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#define DRV_NAME "iTCO_wdt"
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#define DRV_VERSION "1.04"
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#define DRV_VERSION "1.05"
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#define PFX DRV_NAME ": "
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/* Includes */
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@ -236,16 +236,16 @@ MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
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/* Address definitions for the TCO */
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/* TCO base address */
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#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60
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#define TCOBASE iTCO_wdt_private.ACPIBASE + 0x60
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/* SMI Control and Enable Register */
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#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30
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#define SMI_EN iTCO_wdt_private.ACPIBASE + 0x30
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#define TCO_RLD TCOBASE + 0x00 /* TCO Timer Reload and Curr. Value */
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#define TCOv1_TMR TCOBASE + 0x01 /* TCOv1 Timer Initial Value */
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#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
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#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
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#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
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#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
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#define TCO_DAT_IN TCOBASE + 0x02 /* TCO Data In Register */
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#define TCO_DAT_OUT TCOBASE + 0x03 /* TCO Data Out Register */
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#define TCO1_STS TCOBASE + 0x04 /* TCO1 Status Register */
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#define TCO2_STS TCOBASE + 0x06 /* TCO2 Status Register */
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#define TCO1_CNT TCOBASE + 0x08 /* TCO1 Control Register */
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#define TCO2_CNT TCOBASE + 0x0a /* TCO2 Control Register */
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#define TCOv2_TMR TCOBASE + 0x12 /* TCOv2 Timer Initial Value */
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@ -338,7 +338,6 @@ static int iTCO_wdt_unset_NO_REBOOT_bit(void)
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static int iTCO_wdt_start(void)
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{
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unsigned int val;
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unsigned long val32;
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spin_lock(&iTCO_wdt_private.io_lock);
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@ -351,11 +350,6 @@ static int iTCO_wdt_start(void)
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return -EIO;
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}
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/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
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val32 = inl(SMI_EN);
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val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
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outl(val32, SMI_EN);
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/* Force the timer to its reload value by writing to the TCO_RLD
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register */
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if (iTCO_wdt_private.iTCO_version == 2)
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@ -378,7 +372,6 @@ static int iTCO_wdt_start(void)
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static int iTCO_wdt_stop(void)
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{
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unsigned int val;
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unsigned long val32;
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spin_lock(&iTCO_wdt_private.io_lock);
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@ -390,11 +383,6 @@ static int iTCO_wdt_stop(void)
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outw(val, TCO1_CNT);
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val = inw(TCO1_CNT);
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/* Bit 13: TCO_EN -> 1 = Enables the TCO logic to generate SMI# */
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val32 = inl(SMI_EN);
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val32 |= 0x00002000;
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outl(val32, SMI_EN);
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/* Set the NO_REBOOT bit to prevent later reboots, just for sure */
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iTCO_wdt_set_NO_REBOOT_bit();
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@ -649,6 +637,7 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
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int ret;
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u32 base_address;
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unsigned long RCBA;
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unsigned long val32;
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/*
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* Find the ACPI/PM base I/O address which is the base
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@ -695,6 +684,10 @@ static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
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ret = -EIO;
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goto out;
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}
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/* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
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val32 = inl(SMI_EN);
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val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
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outl(val32, SMI_EN);
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/* The TCO I/O registers reside in a 32-byte range pointed to
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by the TCOBASE value */
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