x86: style cleanups for xen assemblies
Make the following style cleanups: * drop unnecessary //#include from xen-asm_32.S * compulsive adding of space after comma * reformat multiline comments Signed-off-by: Tejun Heo <tj@kernel.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Tejun Heo
Ingo Molnar
parent
69b745ff91
commit
130ace11a9
@ -1,14 +1,14 @@
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/*
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Asm versions of Xen pv-ops, suitable for either direct use or inlining.
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The inline versions are the same as the direct-use versions, with the
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pre- and post-amble chopped off.
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This code is encoded for size rather than absolute efficiency,
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with a view to being able to inline as much as possible.
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We only bother with direct forms (ie, vcpu in percpu data) of
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the operations here; the indirect forms are better handled in
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C, since they're generally too large to inline anyway.
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* Asm versions of Xen pv-ops, suitable for either direct use or
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* inlining. The inline versions are the same as the direct-use
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* versions, with the pre- and post-amble chopped off.
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*
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* This code is encoded for size rather than absolute efficiency, with
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* a view to being able to inline as much as possible.
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*
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* We only bother with direct forms (ie, vcpu in percpu data) of the
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* operations here; the indirect forms are better handled in C, since
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* they're generally too large to inline anyway.
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*/
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#include <asm/asm-offsets.h>
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@ -18,17 +18,19 @@
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#include "xen-asm.h"
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/*
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Enable events. This clears the event mask and tests the pending
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event status with one and operation. If there are pending
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events, then enter the hypervisor to get them handled.
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* Enable events. This clears the event mask and tests the pending
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* event status with one and operation. If there are pending events,
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* then enter the hypervisor to get them handled.
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*/
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ENTRY(xen_irq_enable_direct)
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/* Unmask events */
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movb $0, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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/* Preempt here doesn't matter because that will deal with
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any pending interrupts. The pending check may end up being
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run on the wrong CPU, but that doesn't hurt. */
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/*
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* Preempt here doesn't matter because that will deal with any
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* pending interrupts. The pending check may end up being run
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* on the wrong CPU, but that doesn't hurt.
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*/
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/* Test for pending */
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testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
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@ -43,8 +45,8 @@ ENDPATCH(xen_irq_enable_direct)
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/*
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Disabling events is simply a matter of making the event mask
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non-zero.
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* Disabling events is simply a matter of making the event mask
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* non-zero.
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*/
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ENTRY(xen_irq_disable_direct)
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movb $1, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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@ -54,18 +56,18 @@ ENDPATCH(xen_irq_disable_direct)
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RELOC(xen_irq_disable_direct, 0)
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/*
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(xen_)save_fl is used to get the current interrupt enable status.
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Callers expect the status to be in X86_EFLAGS_IF, and other bits
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may be set in the return value. We take advantage of this by
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making sure that X86_EFLAGS_IF has the right value (and other bits
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in that byte are 0), but other bits in the return value are
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undefined. We need to toggle the state of the bit, because
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Xen and x86 use opposite senses (mask vs enable).
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* (xen_)save_fl is used to get the current interrupt enable status.
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* Callers expect the status to be in X86_EFLAGS_IF, and other bits
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* may be set in the return value. We take advantage of this by
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* making sure that X86_EFLAGS_IF has the right value (and other bits
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* in that byte are 0), but other bits in the return value are
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* undefined. We need to toggle the state of the bit, because Xen and
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* x86 use opposite senses (mask vs enable).
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*/
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ENTRY(xen_save_fl_direct)
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testb $0xff, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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setz %ah
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addb %ah,%ah
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addb %ah, %ah
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ENDPATCH(xen_save_fl_direct)
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ret
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ENDPROC(xen_save_fl_direct)
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@ -73,12 +75,11 @@ ENDPATCH(xen_save_fl_direct)
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/*
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In principle the caller should be passing us a value return
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from xen_save_fl_direct, but for robustness sake we test only
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the X86_EFLAGS_IF flag rather than the whole byte. After
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setting the interrupt mask state, it checks for unmasked
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pending events and enters the hypervisor to get them delivered
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if so.
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* In principle the caller should be passing us a value return from
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* xen_save_fl_direct, but for robustness sake we test only the
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* X86_EFLAGS_IF flag rather than the whole byte. After setting the
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* interrupt mask state, it checks for unmasked pending events and
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* enters the hypervisor to get them delivered if so.
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*/
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ENTRY(xen_restore_fl_direct)
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#ifdef CONFIG_X86_64
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@ -87,9 +88,11 @@ ENTRY(xen_restore_fl_direct)
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testb $X86_EFLAGS_IF>>8, %ah
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#endif
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setz PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_mask
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/* Preempt here doesn't matter because that will deal with
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any pending interrupts. The pending check may end up being
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run on the wrong CPU, but that doesn't hurt. */
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/*
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* Preempt here doesn't matter because that will deal with any
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* pending interrupts. The pending check may end up being run
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* on the wrong CPU, but that doesn't hurt.
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*/
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/* check for unmasked and pending */
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cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
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@ -103,8 +106,8 @@ ENDPATCH(xen_restore_fl_direct)
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/*
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Force an event check by making a hypercall,
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but preserve regs before making the call.
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* Force an event check by making a hypercall, but preserve regs
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* before making the call.
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*/
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check_events:
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#ifdef CONFIG_X86_32
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@ -137,4 +140,3 @@ check_events:
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pop %rax
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#endif
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ret
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@ -1,17 +1,16 @@
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/*
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Asm versions of Xen pv-ops, suitable for either direct use or inlining.
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The inline versions are the same as the direct-use versions, with the
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pre- and post-amble chopped off.
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This code is encoded for size rather than absolute efficiency,
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with a view to being able to inline as much as possible.
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We only bother with direct forms (ie, vcpu in pda) of the operations
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here; the indirect forms are better handled in C, since they're
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generally too large to inline anyway.
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* Asm versions of Xen pv-ops, suitable for either direct use or
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* inlining. The inline versions are the same as the direct-use
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* versions, with the pre- and post-amble chopped off.
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*
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* This code is encoded for size rather than absolute efficiency, with
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* a view to being able to inline as much as possible.
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*
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* We only bother with direct forms (ie, vcpu in pda) of the
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* operations here; the indirect forms are better handled in C, since
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* they're generally too large to inline anyway.
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*/
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//#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#include <asm/processor-flags.h>
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#include <asm/segment.h>
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@ -21,8 +20,8 @@
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#include "xen-asm.h"
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/*
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Force an event check by making a hypercall,
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but preserve regs before making the call.
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* Force an event check by making a hypercall, but preserve regs
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* before making the call.
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*/
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check_events:
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push %eax
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@ -35,10 +34,10 @@ check_events:
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ret
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/*
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We can't use sysexit directly, because we're not running in ring0.
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But we can easily fake it up using iret. Assuming xen_sysexit
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is jumped to with a standard stack frame, we can just strip it
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back to a standard iret frame and use iret.
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* We can't use sysexit directly, because we're not running in ring0.
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* But we can easily fake it up using iret. Assuming xen_sysexit is
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* jumped to with a standard stack frame, we can just strip it back to
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* a standard iret frame and use iret.
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*/
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ENTRY(xen_sysexit)
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movl PT_EAX(%esp), %eax /* Shouldn't be necessary? */
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@ -49,33 +48,31 @@ ENTRY(xen_sysexit)
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ENDPROC(xen_sysexit)
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/*
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This is run where a normal iret would be run, with the same stack setup:
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8: eflags
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4: cs
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esp-> 0: eip
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This attempts to make sure that any pending events are dealt
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with on return to usermode, but there is a small window in
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which an event can happen just before entering usermode. If
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the nested interrupt ends up setting one of the TIF_WORK_MASK
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pending work flags, they will not be tested again before
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returning to usermode. This means that a process can end up
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with pending work, which will be unprocessed until the process
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enters and leaves the kernel again, which could be an
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unbounded amount of time. This means that a pending signal or
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reschedule event could be indefinitely delayed.
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The fix is to notice a nested interrupt in the critical
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window, and if one occurs, then fold the nested interrupt into
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the current interrupt stack frame, and re-process it
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iteratively rather than recursively. This means that it will
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exit via the normal path, and all pending work will be dealt
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with appropriately.
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Because the nested interrupt handler needs to deal with the
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current stack state in whatever form its in, we keep things
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simple by only using a single register which is pushed/popped
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on the stack.
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* This is run where a normal iret would be run, with the same stack setup:
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* 8: eflags
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* 4: cs
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* esp-> 0: eip
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*
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* This attempts to make sure that any pending events are dealt with
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* on return to usermode, but there is a small window in which an
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* event can happen just before entering usermode. If the nested
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* interrupt ends up setting one of the TIF_WORK_MASK pending work
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* flags, they will not be tested again before returning to
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* usermode. This means that a process can end up with pending work,
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* which will be unprocessed until the process enters and leaves the
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* kernel again, which could be an unbounded amount of time. This
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* means that a pending signal or reschedule event could be
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* indefinitely delayed.
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*
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* The fix is to notice a nested interrupt in the critical window, and
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* if one occurs, then fold the nested interrupt into the current
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* interrupt stack frame, and re-process it iteratively rather than
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* recursively. This means that it will exit via the normal path, and
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* all pending work will be dealt with appropriately.
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*
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* Because the nested interrupt handler needs to deal with the current
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* stack state in whatever form its in, we keep things simple by only
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* using a single register which is pushed/popped on the stack.
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*/
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ENTRY(xen_iret)
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/* test eflags for special cases */
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@ -85,13 +82,15 @@ ENTRY(xen_iret)
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push %eax
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ESP_OFFSET=4 # bytes pushed onto stack
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/* Store vcpu_info pointer for easy access. Do it this
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way to avoid having to reload %fs */
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/*
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* Store vcpu_info pointer for easy access. Do it this way to
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* avoid having to reload %fs
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*/
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#ifdef CONFIG_SMP
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GET_THREAD_INFO(%eax)
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movl TI_cpu(%eax),%eax
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movl __per_cpu_offset(,%eax,4),%eax
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mov per_cpu__xen_vcpu(%eax),%eax
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movl TI_cpu(%eax), %eax
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movl __per_cpu_offset(,%eax,4), %eax
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mov per_cpu__xen_vcpu(%eax), %eax
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#else
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movl per_cpu__xen_vcpu, %eax
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#endif
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@ -99,37 +98,46 @@ ENTRY(xen_iret)
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/* check IF state we're restoring */
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testb $X86_EFLAGS_IF>>8, 8+1+ESP_OFFSET(%esp)
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/* Maybe enable events. Once this happens we could get a
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recursive event, so the critical region starts immediately
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afterwards. However, if that happens we don't end up
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resuming the code, so we don't have to be worried about
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being preempted to another CPU. */
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/*
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* Maybe enable events. Once this happens we could get a
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* recursive event, so the critical region starts immediately
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* afterwards. However, if that happens we don't end up
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* resuming the code, so we don't have to be worried about
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* being preempted to another CPU.
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*/
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setz XEN_vcpu_info_mask(%eax)
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xen_iret_start_crit:
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/* check for unmasked and pending */
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cmpw $0x0001, XEN_vcpu_info_pending(%eax)
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/* If there's something pending, mask events again so we
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can jump back into xen_hypervisor_callback */
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/*
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* If there's something pending, mask events again so we can
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* jump back into xen_hypervisor_callback
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*/
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sete XEN_vcpu_info_mask(%eax)
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popl %eax
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/* From this point on the registers are restored and the stack
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updated, so we don't need to worry about it if we're preempted */
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/*
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* From this point on the registers are restored and the stack
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* updated, so we don't need to worry about it if we're
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* preempted
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*/
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iret_restore_end:
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/* Jump to hypervisor_callback after fixing up the stack.
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Events are masked, so jumping out of the critical
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region is OK. */
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/*
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* Jump to hypervisor_callback after fixing up the stack.
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* Events are masked, so jumping out of the critical region is
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* OK.
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*/
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je xen_hypervisor_callback
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1: iret
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xen_iret_end_crit:
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.section __ex_table,"a"
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.section __ex_table, "a"
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.align 4
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.long 1b,iret_exc
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.long 1b, iret_exc
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.previous
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hyper_iret:
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@ -139,55 +147,55 @@ hyper_iret:
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.globl xen_iret_start_crit, xen_iret_end_crit
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/*
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This is called by xen_hypervisor_callback in entry.S when it sees
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that the EIP at the time of interrupt was between xen_iret_start_crit
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and xen_iret_end_crit. We're passed the EIP in %eax so we can do
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a more refined determination of what to do.
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The stack format at this point is:
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----------------
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ss : (ss/esp may be present if we came from usermode)
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esp :
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eflags } outer exception info
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cs }
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eip }
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---------------- <- edi (copy dest)
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eax : outer eax if it hasn't been restored
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----------------
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eflags } nested exception info
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cs } (no ss/esp because we're nested
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eip } from the same ring)
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orig_eax }<- esi (copy src)
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- - - - - - - -
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fs }
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es }
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ds } SAVE_ALL state
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eax }
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: :
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ebx }<- esp
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----------------
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In order to deliver the nested exception properly, we need to shift
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everything from the return addr up to the error code so it
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sits just under the outer exception info. This means that when we
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handle the exception, we do it in the context of the outer exception
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rather than starting a new one.
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The only caveat is that if the outer eax hasn't been
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restored yet (ie, it's still on stack), we need to insert
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its value into the SAVE_ALL state before going on, since
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it's usermode state which we eventually need to restore.
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* This is called by xen_hypervisor_callback in entry.S when it sees
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* that the EIP at the time of interrupt was between
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* xen_iret_start_crit and xen_iret_end_crit. We're passed the EIP in
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* %eax so we can do a more refined determination of what to do.
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*
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* The stack format at this point is:
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* ----------------
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* ss : (ss/esp may be present if we came from usermode)
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* esp :
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* eflags } outer exception info
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* cs }
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* eip }
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* ---------------- <- edi (copy dest)
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* eax : outer eax if it hasn't been restored
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* ----------------
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* eflags } nested exception info
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* cs } (no ss/esp because we're nested
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* eip } from the same ring)
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* orig_eax }<- esi (copy src)
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* - - - - - - - -
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* fs }
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* es }
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* ds } SAVE_ALL state
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* eax }
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* : :
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* ebx }<- esp
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* ----------------
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*
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* In order to deliver the nested exception properly, we need to shift
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* everything from the return addr up to the error code so it sits
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* just under the outer exception info. This means that when we
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* handle the exception, we do it in the context of the outer
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* exception rather than starting a new one.
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*
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* The only caveat is that if the outer eax hasn't been restored yet
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* (ie, it's still on stack), we need to insert its value into the
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* SAVE_ALL state before going on, since it's usermode state which we
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* eventually need to restore.
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*/
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ENTRY(xen_iret_crit_fixup)
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/*
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Paranoia: Make sure we're really coming from kernel space.
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One could imagine a case where userspace jumps into the
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critical range address, but just before the CPU delivers a GP,
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it decides to deliver an interrupt instead. Unlikely?
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Definitely. Easy to avoid? Yes. The Intel documents
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explicitly say that the reported EIP for a bad jump is the
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jump instruction itself, not the destination, but some virtual
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environments get this wrong.
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* Paranoia: Make sure we're really coming from kernel space.
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* One could imagine a case where userspace jumps into the
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* critical range address, but just before the CPU delivers a
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* GP, it decides to deliver an interrupt instead. Unlikely?
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* Definitely. Easy to avoid? Yes. The Intel documents
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* explicitly say that the reported EIP for a bad jump is the
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* jump instruction itself, not the destination, but some
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* virtual environments get this wrong.
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*/
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movl PT_CS(%esp), %ecx
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andl $SEGMENT_RPL_MASK, %ecx
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@ -197,15 +205,17 @@ ENTRY(xen_iret_crit_fixup)
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lea PT_ORIG_EAX(%esp), %esi
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lea PT_EFLAGS(%esp), %edi
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/* If eip is before iret_restore_end then stack
|
||||
hasn't been restored yet. */
|
||||
/*
|
||||
* If eip is before iret_restore_end then stack
|
||||
* hasn't been restored yet.
|
||||
*/
|
||||
cmp $iret_restore_end, %eax
|
||||
jae 1f
|
||||
|
||||
movl 0+4(%edi),%eax /* copy EAX (just above top of frame) */
|
||||
movl 0+4(%edi), %eax /* copy EAX (just above top of frame) */
|
||||
movl %eax, PT_EAX(%esp)
|
||||
|
||||
lea ESP_OFFSET(%edi),%edi /* move dest up over saved regs */
|
||||
lea ESP_OFFSET(%edi), %edi /* move dest up over saved regs */
|
||||
|
||||
/* set up the copy */
|
||||
1: std
|
||||
@ -213,6 +223,6 @@ ENTRY(xen_iret_crit_fixup)
|
||||
rep movsl
|
||||
cld
|
||||
|
||||
lea 4(%edi),%esp /* point esp to new frame */
|
||||
lea 4(%edi), %esp /* point esp to new frame */
|
||||
2: jmp xen_do_upcall
|
||||
|
||||
|
||||
@ -1,14 +1,14 @@
|
||||
/*
|
||||
Asm versions of Xen pv-ops, suitable for either direct use or inlining.
|
||||
The inline versions are the same as the direct-use versions, with the
|
||||
pre- and post-amble chopped off.
|
||||
|
||||
This code is encoded for size rather than absolute efficiency,
|
||||
with a view to being able to inline as much as possible.
|
||||
|
||||
We only bother with direct forms (ie, vcpu in pda) of the operations
|
||||
here; the indirect forms are better handled in C, since they're
|
||||
generally too large to inline anyway.
|
||||
* Asm versions of Xen pv-ops, suitable for either direct use or
|
||||
* inlining. The inline versions are the same as the direct-use
|
||||
* versions, with the pre- and post-amble chopped off.
|
||||
*
|
||||
* This code is encoded for size rather than absolute efficiency, with
|
||||
* a view to being able to inline as much as possible.
|
||||
*
|
||||
* We only bother with direct forms (ie, vcpu in pda) of the
|
||||
* operations here; the indirect forms are better handled in C, since
|
||||
* they're generally too large to inline anyway.
|
||||
*/
|
||||
|
||||
#include <asm/errno.h>
|
||||
@ -21,25 +21,25 @@
|
||||
#include "xen-asm.h"
|
||||
|
||||
ENTRY(xen_adjust_exception_frame)
|
||||
mov 8+0(%rsp),%rcx
|
||||
mov 8+8(%rsp),%r11
|
||||
mov 8+0(%rsp), %rcx
|
||||
mov 8+8(%rsp), %r11
|
||||
ret $16
|
||||
|
||||
hypercall_iret = hypercall_page + __HYPERVISOR_iret * 32
|
||||
/*
|
||||
Xen64 iret frame:
|
||||
|
||||
ss
|
||||
rsp
|
||||
rflags
|
||||
cs
|
||||
rip <-- standard iret frame
|
||||
|
||||
flags
|
||||
|
||||
rcx }
|
||||
r11 }<-- pushed by hypercall page
|
||||
rsp -> rax }
|
||||
* Xen64 iret frame:
|
||||
*
|
||||
* ss
|
||||
* rsp
|
||||
* rflags
|
||||
* cs
|
||||
* rip <-- standard iret frame
|
||||
*
|
||||
* flags
|
||||
*
|
||||
* rcx }
|
||||
* r11 }<-- pushed by hypercall page
|
||||
* rsp->rax }
|
||||
*/
|
||||
ENTRY(xen_iret)
|
||||
pushq $0
|
||||
@ -48,8 +48,8 @@ ENDPATCH(xen_iret)
|
||||
RELOC(xen_iret, 1b+1)
|
||||
|
||||
/*
|
||||
sysexit is not used for 64-bit processes, so it's
|
||||
only ever used to return to 32-bit compat userspace.
|
||||
* sysexit is not used for 64-bit processes, so it's only ever used to
|
||||
* return to 32-bit compat userspace.
|
||||
*/
|
||||
ENTRY(xen_sysexit)
|
||||
pushq $__USER32_DS
|
||||
@ -64,10 +64,12 @@ ENDPATCH(xen_sysexit)
|
||||
RELOC(xen_sysexit, 1b+1)
|
||||
|
||||
ENTRY(xen_sysret64)
|
||||
/* We're already on the usermode stack at this point, but still
|
||||
with the kernel gs, so we can easily switch back */
|
||||
/*
|
||||
* We're already on the usermode stack at this point, but
|
||||
* still with the kernel gs, so we can easily switch back
|
||||
*/
|
||||
movq %rsp, PER_CPU_VAR(old_rsp)
|
||||
movq PER_CPU_VAR(kernel_stack),%rsp
|
||||
movq PER_CPU_VAR(kernel_stack), %rsp
|
||||
|
||||
pushq $__USER_DS
|
||||
pushq PER_CPU_VAR(old_rsp)
|
||||
@ -81,8 +83,10 @@ ENDPATCH(xen_sysret64)
|
||||
RELOC(xen_sysret64, 1b+1)
|
||||
|
||||
ENTRY(xen_sysret32)
|
||||
/* We're already on the usermode stack at this point, but still
|
||||
with the kernel gs, so we can easily switch back */
|
||||
/*
|
||||
* We're already on the usermode stack at this point, but
|
||||
* still with the kernel gs, so we can easily switch back
|
||||
*/
|
||||
movq %rsp, PER_CPU_VAR(old_rsp)
|
||||
movq PER_CPU_VAR(kernel_stack), %rsp
|
||||
|
||||
@ -98,28 +102,27 @@ ENDPATCH(xen_sysret32)
|
||||
RELOC(xen_sysret32, 1b+1)
|
||||
|
||||
/*
|
||||
Xen handles syscall callbacks much like ordinary exceptions,
|
||||
which means we have:
|
||||
- kernel gs
|
||||
- kernel rsp
|
||||
- an iret-like stack frame on the stack (including rcx and r11):
|
||||
ss
|
||||
rsp
|
||||
rflags
|
||||
cs
|
||||
rip
|
||||
r11
|
||||
rsp-> rcx
|
||||
|
||||
In all the entrypoints, we undo all that to make it look
|
||||
like a CPU-generated syscall/sysenter and jump to the normal
|
||||
entrypoint.
|
||||
* Xen handles syscall callbacks much like ordinary exceptions, which
|
||||
* means we have:
|
||||
* - kernel gs
|
||||
* - kernel rsp
|
||||
* - an iret-like stack frame on the stack (including rcx and r11):
|
||||
* ss
|
||||
* rsp
|
||||
* rflags
|
||||
* cs
|
||||
* rip
|
||||
* r11
|
||||
* rsp->rcx
|
||||
*
|
||||
* In all the entrypoints, we undo all that to make it look like a
|
||||
* CPU-generated syscall/sysenter and jump to the normal entrypoint.
|
||||
*/
|
||||
|
||||
.macro undo_xen_syscall
|
||||
mov 0*8(%rsp),%rcx
|
||||
mov 1*8(%rsp),%r11
|
||||
mov 5*8(%rsp),%rsp
|
||||
mov 0*8(%rsp), %rcx
|
||||
mov 1*8(%rsp), %r11
|
||||
mov 5*8(%rsp), %rsp
|
||||
.endm
|
||||
|
||||
/* Normal 64-bit system call target */
|
||||
@ -146,7 +149,7 @@ ENDPROC(xen_sysenter_target)
|
||||
|
||||
ENTRY(xen_syscall32_target)
|
||||
ENTRY(xen_sysenter_target)
|
||||
lea 16(%rsp), %rsp /* strip %rcx,%r11 */
|
||||
lea 16(%rsp), %rsp /* strip %rcx, %r11 */
|
||||
mov $-ENOSYS, %rax
|
||||
pushq $VGCF_in_syscall
|
||||
jmp hypercall_iret
|
||||
|
||||
Loading…
Reference in New Issue
Block a user