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spi: spi-fsl-dspi: Add support for LS1028A

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This is similar to the DSPI instantiation on LS1028A, except that:
 - The A-011218 erratum has been fixed, so DMA works
 - The endianness is different, which has implications on XSPI mode

Some benchmarking with the following command:

spidev_test --device /dev/spidev2.0 --bpw 8 --size 256 --cpha --iter 10000000 --speed 20000000

shows that in DMA mode, it can achieve around 2400 kbps, and in XSPI
mode, the same command goes up to 4700 kbps. This is somewhat to be
expected, since the DMA buffer size is extremely small at 8 bytes, the
winner becomes whomever can prepare the buffers for transmission
quicker, and DMA mode has higher overhead there. So XSPI FIFO mode has
been chosen as the operating mode for this chip.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20200318001603.9650-11-olteanv@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vladimir Oltean 2020-03-18 02:16:01 +02:00 committed by Mark Brown
parent 5b342c5ab7
commit 138f56ef91
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GPG Key ID: 24D68B725D5487D0
1 changed files with 9 additions and 0 deletions
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9
drivers/spi/spi-fsl-dspi.c
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@ -124,6 +124,7 @@ struct fsl_dspi_devtype_data {
enum {
LS1021A,
LS1012A,
LS1028A,
LS1043A,
LS1046A,
LS2080A,
@ -151,6 +152,11 @@ static const struct fsl_dspi_devtype_data devtype_data[] = {
.max_clock_factor = 8,
.fifo_size = 16,
},
[LS1028A] = {
.trans_mode = DSPI_XSPI_MODE,
.max_clock_factor = 8,
.fifo_size = 4,
},
[LS1043A] = {
/* Has A-011218 DMA erratum */
.trans_mode = DSPI_XSPI_MODE,
@ -1050,6 +1056,9 @@ static const struct of_device_id fsl_dspi_dt_ids[] = {
}, {
.compatible = "fsl,ls1012a-dspi",
.data = &devtype_data[LS1012A],
}, {
.compatible = "fsl,ls1028a-dspi",
.data = &devtype_data[LS1028A],
}, {
.compatible = "fsl,ls1043a-dspi",
.data = &devtype_data[LS1043A],