x86: cpu/common*.c, merge display_cacheinfo()
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
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@ -285,6 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size = (ecx>>24) + (edx>>24);
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#ifdef CONFIG_X86_64
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/* On K8 L1 TLB is inclusive, so don't count it */
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c->x86_tlbsize = 0;
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#endif
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}
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if (n < 0x80000006) /* Some chips just has a large L1. */
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@ -293,6 +297,9 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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l2size = ecx >> 16;
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#ifdef CONFIG_X86_64
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c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
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#else
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/* do processor-specific cache resizing */
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if (this_cpu->c_size_cache)
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l2size = this_cpu->c_size_cache(c, l2size);
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@ -303,6 +310,7 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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if (l2size == 0)
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return; /* Again, no L2 cache is possible */
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#endif
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c->x86_cache_size = l2size;
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@ -285,8 +285,10 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
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c->x86_cache_size = (ecx>>24) + (edx>>24);
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#ifdef CONFIG_X86_64
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/* On K8 L1 TLB is inclusive, so don't count it */
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c->x86_tlbsize = 0;
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#endif
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}
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if (n < 0x80000006) /* Some chips just has a large L1. */
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@ -294,7 +296,22 @@ void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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l2size = ecx >> 16;
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#ifdef CONFIG_X86_64
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c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
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#else
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/* do processor-specific cache resizing */
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if (this_cpu->c_size_cache)
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l2size = this_cpu->c_size_cache(c, l2size);
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/* Allow user to override all this if necessary. */
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if (cachesize_override != -1)
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l2size = cachesize_override;
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if (l2size == 0)
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return; /* Again, no L2 cache is possible */
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#endif
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c->x86_cache_size = l2size;
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