powerpc/8xx: Start using dcbX instructions in various copy routines
Now that 8xx can fixup dcbX instructions, start using them where possible like every other PowerPc arch do. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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0c4661698c
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@ -502,15 +502,7 @@ _GLOBAL(clear_pages)
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li r0,PAGE_SIZE/L1_CACHE_BYTES
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slw r0,r0,r4
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mtctr r0
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#ifdef CONFIG_8xx
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li r4, 0
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1: stw r4, 0(r3)
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stw r4, 4(r3)
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stw r4, 8(r3)
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stw r4, 12(r3)
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#else
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1: dcbz 0,r3
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#endif
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addi r3,r3,L1_CACHE_BYTES
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bdnz 1b
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blr
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@ -535,15 +527,6 @@ _GLOBAL(copy_page)
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addi r3,r3,-4
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addi r4,r4,-4
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#ifdef CONFIG_8xx
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/* don't use prefetch on 8xx */
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li r0,4096/L1_CACHE_BYTES
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mtctr r0
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1: COPY_16_BYTES
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bdnz 1b
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blr
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#else /* not 8xx, we can prefetch */
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li r5,4
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#if MAX_COPY_PREFETCH > 1
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@ -584,7 +567,6 @@ _GLOBAL(copy_page)
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li r0,MAX_COPY_PREFETCH
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li r11,4
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b 2b
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#endif /* CONFIG_8xx */
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/*
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* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
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@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero)
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bdnz 4b
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3: mtctr r9
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li r7,4
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#if !defined(CONFIG_8xx)
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10: dcbz r7,r6
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#else
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10: stw r4, 4(r6)
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stw r4, 8(r6)
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stw r4, 12(r6)
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stw r4, 16(r6)
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#if CACHE_LINE_SIZE >= 32
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stw r4, 20(r6)
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stw r4, 24(r6)
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stw r4, 28(r6)
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stw r4, 32(r6)
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#endif /* CACHE_LINE_SIZE */
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#endif
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addi r6,r6,CACHELINE_BYTES
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bdnz 10b
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clrlwi r5,r8,32-LG_CACHELINE_BYTES
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@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy)
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mtctr r0
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beq 63f
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53:
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#if !defined(CONFIG_8xx)
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dcbz r11,r6
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#endif
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COPY_16_BYTES
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#if L1_CACHE_BYTES >= 32
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COPY_16_BYTES
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@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user)
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li r11,4
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beq 63f
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#ifdef CONFIG_8xx
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/* Don't use prefetch on 8xx */
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mtctr r0
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li r0,0
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53: COPY_16_BYTES_WITHEX(0)
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bdnz 53b
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#else /* not CONFIG_8xx */
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/* Here we decide how far ahead to prefetch the source */
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li r3,4
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cmpwi r0,1
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@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user)
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li r3,4
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li r7,0
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bne 114b
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#endif /* CONFIG_8xx */
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63: srwi. r0,r5,2
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mtctr r0
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