clk: ti: drop locking code from mux/divider drivers
TI's mux and divider clock drivers do not require locking and they do not initialize internal spinlocks. This code was occasionally copy-posted from generic mux/divider drivers. So remove it. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -214,7 +214,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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{
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struct clk_divider *divider;
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unsigned int div, value;
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unsigned long flags = 0;
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u32 val;
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if (!hw || !rate)
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@ -228,9 +227,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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if (value > div_mask(divider))
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value = div_mask(divider);
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if (divider->lock)
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spin_lock_irqsave(divider->lock, flags);
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if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
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val = div_mask(divider) << (divider->shift + 16);
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} else {
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@ -240,9 +236,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
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val |= value << divider->shift;
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ti_clk_ll_ops->clk_writel(val, divider->reg);
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if (divider->lock)
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spin_unlock_irqrestore(divider->lock, flags);
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return 0;
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}
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@ -256,8 +249,7 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name,
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unsigned long flags, void __iomem *reg,
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u8 shift, u8 width, u8 clk_divider_flags,
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const struct clk_div_table *table,
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spinlock_t *lock)
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const struct clk_div_table *table)
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{
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struct clk_divider *div;
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struct clk *clk;
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@ -288,7 +280,6 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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div->shift = shift;
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div->width = width;
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div->flags = clk_divider_flags;
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div->lock = lock;
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div->hw.init = &init;
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div->table = table;
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@ -421,7 +412,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup)
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clk = _register_divider(NULL, setup->name, div->parent,
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flags, (void __iomem *)reg, div->bit_shift,
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width, div_flags, table, NULL);
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width, div_flags, table);
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if (IS_ERR(clk))
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kfree(table);
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@ -584,8 +575,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node)
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goto cleanup;
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clk = _register_divider(NULL, node->name, parent_name, flags, reg,
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shift, width, clk_divider_flags, table,
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NULL);
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shift, width, clk_divider_flags, table);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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@ -69,7 +69,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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u32 val;
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unsigned long flags = 0;
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if (mux->table) {
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index = mux->table[index];
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@ -81,9 +80,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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index++;
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}
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if (mux->lock)
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spin_lock_irqsave(mux->lock, flags);
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if (mux->flags & CLK_MUX_HIWORD_MASK) {
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val = mux->mask << (mux->shift + 16);
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} else {
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@ -93,9 +89,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
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val |= index << mux->shift;
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ti_clk_ll_ops->clk_writel(val, mux->reg);
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if (mux->lock)
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spin_unlock_irqrestore(mux->lock, flags);
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return 0;
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}
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@ -109,7 +102,7 @@ static struct clk *_register_mux(struct device *dev, const char *name,
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const char **parent_names, u8 num_parents,
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unsigned long flags, void __iomem *reg,
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u8 shift, u32 mask, u8 clk_mux_flags,
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u32 *table, spinlock_t *lock)
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u32 *table)
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{
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struct clk_mux *mux;
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struct clk *clk;
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@ -133,7 +126,6 @@ static struct clk *_register_mux(struct device *dev, const char *name,
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mux->shift = shift;
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mux->mask = mask;
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mux->flags = clk_mux_flags;
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mux->lock = lock;
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mux->table = table;
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mux->hw.init = &init;
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@ -175,7 +167,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup)
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return _register_mux(NULL, setup->name, mux->parents, mux->num_parents,
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flags, (void __iomem *)reg, mux->bit_shift, mask,
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mux_flags, NULL, NULL);
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mux_flags, NULL);
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}
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/**
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@ -227,8 +219,7 @@ static void of_mux_clk_setup(struct device_node *node)
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mask = (1 << fls(mask)) - 1;
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clk = _register_mux(NULL, node->name, parent_names, num_parents,
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flags, reg, shift, mask, clk_mux_flags, NULL,
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NULL);
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flags, reg, shift, mask, clk_mux_flags, NULL);
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if (!IS_ERR(clk))
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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