STi reset controller updates for v3.19.
This tag adds support to STiH407 reset controllers: 1. st,stih407-powerdown 2. st,stih407-softreset 3. st,stih407-picophyreset -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUU3rHAAoJEMo4jShGhw+JFhQQANFvZotCJQdPV6i60Yca20FJ /cqMb97w34NhilGwxHxT1cXoE5JccTvE2XauVFzfcE+EpTILjhzEM5/k4Lw9aZmk 0PMvGHZgx/8uhZ3UQqShLvP7XsFEiLzm/isHUrgHjDJE+uBCUVt3JWu4W2BtO+qU RPz5+oE2HW6D0Wh0LdL0EOW8lcITSA9JH8+0baoVLJCP4lsuDJJe+ktGEiSmAlUM Ob3++EvyZM1PGoyiqM2Z/hwShttQPb0X8uU60rFMUwd/s3DXw0L2pXX33nELlCk8 oT/FSg4iwOwg3SnY1IqfNMVyj6KAHDgMz27ebtukM+1XV6vinkwQ6/v7kq47c5at SdYtpGO8y4u+/gKd7fOuCPUR2Xa1p2wG7DqRpvd3Ld16QuSb6alKJvxX5y4xX1/N sTjZ8bbeqzEvQqIFUH956/AbfB9JeCVRQAFIbyGSnRcdIMGgcD+KbZ4LMM2ZlMaR iNbMzfpZf7EPrRFza51+91AbMJmwS50t38YosTI3axtuwLSqfjB/R/57MY+guies krwmfBFOY/E0elMwXBxQypOHlpuTQINO8lImkky3AVQOExA5NVGn0ikQrIjZ39Ch oTK4BYdgvqIlorlfDrPDZGOK+uZnWkfN55P19W0yfLjlLjva9g57A/Qeeg1hfisI OqgXf6Y1TLCNCWG7iuTJ =aZN5 -----END PGP SIGNATURE----- Merge tag 'sti-reset-for-v3.19-1' of git://git.stlinux.com/devel/kernel/linux-sti into reset/for_v3.19 STi reset controller updates for v3.19. This tag adds support to STiH407 reset controllers: 1. st,stih407-powerdown 2. st,stih407-softreset 3. st,stih407-picophyreset
This commit is contained in:
Philipp Zabel
commit
1a5f77d395
@ -0,0 +1,42 @@
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STMicroelectronics STi family Sysconfig Picophy SoftReset Controller
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=============================================================================
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This binding describes a reset controller device that is used to enable and
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disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
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the STi family SoC system configuration registers.
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The actual action taken when softreset is asserted is hardware dependent.
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However, when asserted it may not be possible to access the hardware's
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registers and after an assert/deassert sequence the hardware's previous state
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may no longer be valid.
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Please refer to Documentation/devicetree/bindings/reset/reset.txt
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for common reset controller binding usage.
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Required properties:
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- compatible: Should be "st,stih407-picophyreset"
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- #reset-cells: 1, see below
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Example:
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picophyreset: picophyreset-controller {
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compatible = "st,stih407-picophyreset";
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#reset-cells = <1>;
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};
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Specifying picophyreset control of devices
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=======================================
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Device nodes should specify the reset channel required in their "resets"
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property, containing a phandle to the picophyreset device node and an
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index specifying which channel to use, as described in
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Documentation/devicetree/bindings/reset/reset.txt.
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Example:
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usb2_picophy0: usbpicophy@0 {
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resets = <&picophyreset STIH407_PICOPHY0_RESET>;
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};
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Macro definitions for the supported reset channels can be found in:
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include/dt-bindings/reset-controller/stih407-resets.h
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@ -12,4 +12,8 @@ config STIH416_RESET
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bool
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select STI_RESET_SYSCFG
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config STIH407_RESET
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bool
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select STI_RESET_SYSCFG
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endif
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@ -2,3 +2,4 @@ obj-$(CONFIG_STI_RESET_SYSCFG) += reset-syscfg.o
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obj-$(CONFIG_STIH415_RESET) += reset-stih415.o
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obj-$(CONFIG_STIH416_RESET) += reset-stih416.o
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obj-$(CONFIG_STIH407_RESET) += reset-stih407.o
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158
drivers/reset/sti/reset-stih407.c
Normal file
158
drivers/reset/sti/reset-stih407.c
Normal file
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/*
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* Copyright (C) 2014 STMicroelectronics (R&D) Limited
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* Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/reset-controller/stih407-resets.h>
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#include "reset-syscfg.h"
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/* STiH407 Peripheral powerdown definitions. */
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static const char stih407_core[] = "st,stih407-core-syscfg";
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static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
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static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
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#define STIH407_PDN_0(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
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#define STIH407_PDN_1(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
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#define STIH407_PDN_ETH(_bit, _stat) \
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_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
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/* Powerdown requests control 0 */
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#define SYSCFG_5000 0x0
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#define SYSSTAT_5500 0x7d0
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/* Powerdown requests control 1 (High Speed Links) */
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#define SYSCFG_5001 0x4
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#define SYSSTAT_5501 0x7d4
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/* Ethernet powerdown/status/reset */
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#define SYSCFG_4032 0x80
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#define SYSSTAT_4520 0x820
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#define SYSCFG_4002 0x8
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static const struct syscfg_reset_channel_data stih407_powerdowns[] = {
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[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
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[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
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[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
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[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
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[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
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[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
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[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
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[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
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[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
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[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
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};
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/* Reset Generator control 0/1 */
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#define SYSCFG_5131 0x20c
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#define SYSCFG_5132 0x210
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#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
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#define STIH407_SRST_CORE(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
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#define STIH407_SRST_SBC(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
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#define STIH407_SRST_LPM(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
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static const struct syscfg_reset_channel_data stih407_softresets[] = {
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[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
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[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
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[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
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[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
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[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
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[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
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[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
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[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
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[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
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[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
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[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
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[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
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[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
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[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
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[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
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[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
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[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
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[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
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[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
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[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
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[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
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[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
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[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
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[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
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[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
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[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
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[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
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[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
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[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
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};
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/* PicoPHY reset/control */
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#define SYSCFG_5061 0x0f4
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static const struct syscfg_reset_channel_data stih407_picophyresets[] = {
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[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
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[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
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[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
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};
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static const struct syscfg_reset_controller_data stih407_powerdown_controller = {
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.wait_for_ack = true,
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.nr_channels = ARRAY_SIZE(stih407_powerdowns),
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.channels = stih407_powerdowns,
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};
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static const struct syscfg_reset_controller_data stih407_softreset_controller = {
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.wait_for_ack = false,
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.active_low = true,
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.nr_channels = ARRAY_SIZE(stih407_softresets),
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.channels = stih407_softresets,
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};
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static const struct syscfg_reset_controller_data stih407_picophyreset_controller = {
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.wait_for_ack = false,
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.nr_channels = ARRAY_SIZE(stih407_picophyresets),
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.channels = stih407_picophyresets,
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};
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static struct of_device_id stih407_reset_match[] = {
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{
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.compatible = "st,stih407-powerdown",
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.data = &stih407_powerdown_controller,
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},
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{
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.compatible = "st,stih407-softreset",
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.data = &stih407_softreset_controller,
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},
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{
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.compatible = "st,stih407-picophyreset",
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.data = &stih407_picophyreset_controller,
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},
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{ /* sentinel */ },
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};
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static struct platform_driver stih407_reset_driver = {
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.probe = syscfg_reset_probe,
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.driver = {
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.name = "reset-stih407",
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.of_match_table = stih407_reset_match,
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},
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};
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static int __init stih407_reset_init(void)
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{
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return platform_driver_register(&stih407_reset_driver);
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}
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arch_initcall(stih407_reset_init);
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61
include/dt-bindings/reset-controller/stih407-resets.h
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61
include/dt-bindings/reset-controller/stih407-resets.h
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/*
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* This header provides constants for the reset controller
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* based peripheral powerdown requests on the STMicroelectronics
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* STiH407 SoC.
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*/
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#ifndef _DT_BINDINGS_RESET_CONTROLLER_STIH407
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#define _DT_BINDINGS_RESET_CONTROLLER_STIH407
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/* Powerdown requests control 0 */
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#define STIH407_EMISS_POWERDOWN 0
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#define STIH407_NAND_POWERDOWN 1
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/* Synp GMAC PowerDown */
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#define STIH407_ETH1_POWERDOWN 2
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/* Powerdown requests control 1 */
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#define STIH407_USB3_POWERDOWN 3
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#define STIH407_USB2_PORT1_POWERDOWN 4
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#define STIH407_USB2_PORT0_POWERDOWN 5
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#define STIH407_PCIE1_POWERDOWN 6
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#define STIH407_PCIE0_POWERDOWN 7
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#define STIH407_SATA1_POWERDOWN 8
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#define STIH407_SATA0_POWERDOWN 9
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/* Reset defines */
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#define STIH407_ETH1_SOFTRESET 0
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#define STIH407_MMC1_SOFTRESET 1
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#define STIH407_PICOPHY_SOFTRESET 2
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#define STIH407_IRB_SOFTRESET 3
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#define STIH407_PCIE0_SOFTRESET 4
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#define STIH407_PCIE1_SOFTRESET 5
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#define STIH407_SATA0_SOFTRESET 6
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#define STIH407_SATA1_SOFTRESET 7
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#define STIH407_MIPHY0_SOFTRESET 8
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#define STIH407_MIPHY1_SOFTRESET 9
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#define STIH407_MIPHY2_SOFTRESET 10
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#define STIH407_SATA0_PWR_SOFTRESET 11
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#define STIH407_SATA1_PWR_SOFTRESET 12
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#define STIH407_DELTA_SOFTRESET 13
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#define STIH407_BLITTER_SOFTRESET 14
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#define STIH407_HDTVOUT_SOFTRESET 15
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#define STIH407_HDQVDP_SOFTRESET 16
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#define STIH407_VDP_AUX_SOFTRESET 17
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#define STIH407_COMPO_SOFTRESET 18
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#define STIH407_HDMI_TX_PHY_SOFTRESET 19
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#define STIH407_JPEG_DEC_SOFTRESET 20
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#define STIH407_VP8_DEC_SOFTRESET 21
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#define STIH407_GPU_SOFTRESET 22
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#define STIH407_HVA_SOFTRESET 23
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#define STIH407_ERAM_HVA_SOFTRESET 24
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#define STIH407_LPM_SOFTRESET 25
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#define STIH407_KEYSCAN_SOFTRESET 26
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#define STIH407_USB2_PORT0_SOFTRESET 27
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#define STIH407_USB2_PORT1_SOFTRESET 28
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/* Picophy reset defines */
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#define STIH407_PICOPHY0_RESET 0
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#define STIH407_PICOPHY1_RESET 1
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#define STIH407_PICOPHY2_RESET 2
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_STIH407 */
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