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MIPS: Decode c0_config4 for large TLBs.

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For processors that have more than 64 TLBs, we need to decode both
config1 and config4 to determine the total number TLBs.

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
To: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/866/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney 2010-01-22 14:41:15 -08:00 committed by Ralf Baechle
parent 2a880986d8
commit 1b362e3e35
2 changed files with 19 additions and 0 deletions
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4
arch/mips/include/asm/mipsregs.h
View File

@ -576,6 +576,10 @@
#define MIPS_CONF3_DSP (_ULCAST_(1) << 10) #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
#define MIPS_CONF7_WII (_ULCAST_(1) << 31) #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
#define MIPS_CONF7_RPS (_ULCAST_(1) << 2) #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)

15
arch/mips/kernel/cpu-probe.c
View File

@ -700,6 +700,19 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
return config3 & MIPS_CONF_M; return config3 & MIPS_CONF_M;
} }
static inline unsigned int decode_config4(struct cpuinfo_mips *c)
{
unsigned int config4;
config4 = read_c0_config4();
if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
&& cpu_has_tlb)
c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
return config4 & MIPS_CONF_M;
}
static void __cpuinit decode_configs(struct cpuinfo_mips *c) static void __cpuinit decode_configs(struct cpuinfo_mips *c)
{ {
int ok; int ok;
@ -718,6 +731,8 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c)
ok = decode_config2(c); ok = decode_config2(c);
if (ok) if (ok)
ok = decode_config3(c); ok = decode_config3(c);
if (ok)
ok = decode_config4(c);
mips_probe_watch_registers(c); mips_probe_watch_registers(c);
} }