cxgb4i: set the initial sequence number
set the initial sequence number so the 1st byte of payload is aligned on the 8-byte boundary. Signed-off-by: Karen Xie <kxie@chelsio.com> Reviewed-by: Mike Christie <michaelc@cs.wisc.edu> Signed-off-by: James Bottomley <JBottomley@Odin.com>
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@ -200,9 +200,9 @@ static void send_act_open_req(struct cxgbi_sock *csk, struct sk_buff *skb,
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SMAC_SEL_V(csk->smac_idx) |
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ULP_MODE_V(ULP_MODE_ISCSI) |
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RCV_BUFSIZ_V(csk->rcv_win >> 10);
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opt2 = RX_CHANNEL_V(0) |
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RSS_QUEUE_VALID_F |
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(RX_FC_DISABLE_F) |
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RSS_QUEUE_V(csk->rss_qid);
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if (is_t4(lldi->adapter_type)) {
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@ -231,6 +231,7 @@ static void send_act_open_req(struct cxgbi_sock *csk, struct sk_buff *skb,
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} else {
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struct cpl_t5_act_open_req *req =
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(struct cpl_t5_act_open_req *)skb->head;
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u32 isn = (prandom_u32() & ~7UL) - 1;
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INIT_TP_WR(req, 0);
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OPCODE_TID(req) = cpu_to_be32(MK_OPCODE_TID(CPL_ACT_OPEN_REQ,
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@ -244,7 +245,10 @@ static void send_act_open_req(struct cxgbi_sock *csk, struct sk_buff *skb,
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cxgb4_select_ntuple(
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csk->cdev->ports[csk->port_id],
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csk->l2t)));
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opt2 |= 1 << 31;
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req->rsvd = cpu_to_be32(isn);
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opt2 |= T5_ISS_VALID;
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opt2 |= T5_OPT_2_VALID_F;
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req->opt2 = cpu_to_be32(opt2);
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log_debug(1 << CXGBI_DBG_TOE | 1 << CXGBI_DBG_SOCK,
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@ -23,6 +23,8 @@
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#define CXGB4I_TX_HEADER_LEN \
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(sizeof(struct fw_ofld_tx_data_wr) + sizeof(struct sge_opaque_hdr))
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#define T5_ISS_VALID (1 << 18)
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struct ulptx_idata {
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__be32 cmd_more;
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__be32 len;
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