[ARM] 4719/1: S3C2412: Update SPI register definitions for the S3C2412
Add S3C2412 register definitions. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -17,6 +17,7 @@
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#define S3C2410_SPCON (0x00)
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#define S3C2412_SPCON_DIRC_RX (1<<7)
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#define S3C2410_SPCON_SMOD_DMA (2<<5) /* DMA mode */
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#define S3C2410_SPCON_SMOD_INT (1<<5) /* interrupt mode */
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#define S3C2410_SPCON_SMOD_POLL (0<<5) /* polling mode */
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@ -37,7 +38,7 @@
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#define S3C2410_SPSTA_DCOL (1<<2) /* Data Collision Error */
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#define S3C2410_SPSTA_MULD (1<<1) /* Multi Master Error */
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#define S3C2410_SPSTA_READY (1<<0) /* Data Tx/Rx ready */
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#define S3C2412_SPSTA_READY_ORG (1<<3)
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#define S3C2410_SPPIN (0x08)
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@ -46,9 +47,13 @@
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#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
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#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
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#define S3C2410_SPPRE (0x0C)
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#define S3C2410_SPTDAT (0x10)
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#define S3C2410_SPRDAT (0x14)
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#define S3C2412_TXFIFO (0x18)
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#define S3C2412_RXFIFO (0x18)
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#define S3C2412_SPFIC (0x24)
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#endif /* __ASM_ARCH_REGS_SPI_H */
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