Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc
Pull sparc fixes from David Miller: 1) Some command cases of semtimedop() not even handled due to miscoded comparison on sparc64. From Rob Gardner. 2) Due to two bugs, /proc/kcore wan't working properly on sparc. 3) Make sure fatal traps stop all running cpus, from Dave Kleikamp. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc: sparc: Fix /proc/kcore sparc: semtimedop() unreachable due to comparison error sparc: io_64.h: Replace io function-link macros sparc64: fatal trap should stop all cpus arch: sparc: kernel: starfire.c: Remove unused function arch: sparc: kernel: traps_64.c: Remove some unused functions
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commit
22283c8260
@ -86,6 +86,9 @@ config ARCH_DEFCONFIG
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default "arch/sparc/configs/sparc32_defconfig" if SPARC32
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default "arch/sparc/configs/sparc64_defconfig" if SPARC64
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config ARCH_PROC_KCORE_TEXT
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def_bool y
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config IOMMU_HELPER
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bool
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default y if SPARC64
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@ -407,16 +407,16 @@ static inline void iounmap(volatile void __iomem *addr)
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{
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}
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#define ioread8(X) readb(X)
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#define ioread16(X) readw(X)
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#define ioread16be(X) __raw_readw(X)
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#define ioread32(X) readl(X)
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#define ioread32be(X) __raw_readl(X)
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#define iowrite8(val,X) writeb(val,X)
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#define iowrite16(val,X) writew(val,X)
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#define iowrite16be(val,X) __raw_writew(val,X)
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#define iowrite32(val,X) writel(val,X)
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#define iowrite32be(val,X) __raw_writel(val,X)
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#define ioread8 readb
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#define ioread16 readw
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#define ioread16be __raw_readw
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#define ioread32 readl
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#define ioread32be __raw_readl
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#define iowrite8 writeb
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#define iowrite16 writew
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#define iowrite16be __raw_writew
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#define iowrite32 writel
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#define iowrite32be __raw_writel
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/* Create a virtual mapping cookie for an IO port range */
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void __iomem *ioport_map(unsigned long port, unsigned int nr);
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@ -12,7 +12,6 @@
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extern int this_is_starfire;
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void check_if_starfire(void);
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int starfire_hard_smp_processor_id(void);
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void starfire_hookup(int);
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unsigned int starfire_translate(unsigned long imap, unsigned int upaid);
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@ -98,11 +98,7 @@ void sun4v_do_mna(struct pt_regs *regs,
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void do_privop(struct pt_regs *regs);
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void do_privact(struct pt_regs *regs);
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void do_cee(struct pt_regs *regs);
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void do_cee_tl1(struct pt_regs *regs);
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void do_dae_tl1(struct pt_regs *regs);
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void do_iae_tl1(struct pt_regs *regs);
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void do_div0_tl1(struct pt_regs *regs);
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void do_fpdis_tl1(struct pt_regs *regs);
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void do_fpieee_tl1(struct pt_regs *regs);
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void do_fpother_tl1(struct pt_regs *regs);
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void do_ill_tl1(struct pt_regs *regs);
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@ -1406,11 +1406,32 @@ void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
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scheduler_ipi();
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}
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/* This is a nop because we capture all other cpus
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* anyways when making the PROM active.
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*/
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static void stop_this_cpu(void *dummy)
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{
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prom_stopself();
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}
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void smp_send_stop(void)
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{
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int cpu;
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if (tlb_type == hypervisor) {
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for_each_online_cpu(cpu) {
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if (cpu == smp_processor_id())
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continue;
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#ifdef CONFIG_SUN_LDOMS
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if (ldom_domaining_enabled) {
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unsigned long hv_err;
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hv_err = sun4v_cpu_stop(cpu);
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if (hv_err)
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printk(KERN_ERR "sun4v_cpu_stop() "
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"failed err=%lu\n", hv_err);
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} else
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#endif
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prom_stopcpu_cpuid(cpu);
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}
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} else
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smp_call_function(stop_this_cpu, NULL, 0);
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}
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/**
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@ -28,11 +28,6 @@ void check_if_starfire(void)
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this_is_starfire = 1;
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}
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int starfire_hard_smp_processor_id(void)
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{
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return upa_readl(0x1fff40000d0UL);
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}
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/*
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* Each Starfire board has 32 registers which perform translation
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* and delivery of traditional interrupt packets into the extended
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@ -333,7 +333,7 @@ SYSCALL_DEFINE6(sparc_ipc, unsigned int, call, int, first, unsigned long, second
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long err;
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/* No need for backward compatibility. We can start fresh... */
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if (call <= SEMCTL) {
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if (call <= SEMTIMEDOP) {
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switch (call) {
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case SEMOP:
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err = sys_semtimedop(first, ptr,
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@ -2427,6 +2427,8 @@ void __noreturn die_if_kernel(char *str, struct pt_regs *regs)
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}
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user_instruction_dump ((unsigned int __user *) regs->tpc);
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}
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if (panic_on_oops)
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panic("Fatal exception");
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if (regs->tstate & TSTATE_PRIV)
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do_exit(SIGKILL);
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do_exit(SIGSEGV);
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@ -2564,27 +2566,6 @@ void do_cee(struct pt_regs *regs)
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die_if_kernel("TL0: Cache Error Exception", regs);
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}
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void do_cee_tl1(struct pt_regs *regs)
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{
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exception_enter();
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dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
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die_if_kernel("TL1: Cache Error Exception", regs);
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}
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void do_dae_tl1(struct pt_regs *regs)
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{
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exception_enter();
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dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
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die_if_kernel("TL1: Data Access Exception", regs);
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}
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void do_iae_tl1(struct pt_regs *regs)
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{
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exception_enter();
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dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
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die_if_kernel("TL1: Instruction Access Exception", regs);
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}
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void do_div0_tl1(struct pt_regs *regs)
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{
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exception_enter();
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@ -2592,13 +2573,6 @@ void do_div0_tl1(struct pt_regs *regs)
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die_if_kernel("TL1: DIV0 Exception", regs);
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}
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void do_fpdis_tl1(struct pt_regs *regs)
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{
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exception_enter();
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dump_tl1_traplog((struct tl1_traplog *)(regs + 1));
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die_if_kernel("TL1: FPU Disabled", regs);
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}
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void do_fpieee_tl1(struct pt_regs *regs)
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{
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exception_enter();
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@ -2820,7 +2820,7 @@ static int __init report_memory(void)
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return 0;
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}
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device_initcall(report_memory);
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arch_initcall(report_memory);
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#ifdef CONFIG_SMP
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#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
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