pwm: atmel-hlcdc: Convert to the atomic PWM API
Implement the ->apply() hook and drop the ->enable(), ->disable, ->set_polarity and ->config() ones. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
This commit is contained in:
Boris Brezillon
Thierry Reding
parent
c1ae3cfa0e
commit
2267517cd3
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@ -49,162 +49,137 @@ static inline struct atmel_hlcdc_pwm *to_atmel_hlcdc_pwm(struct pwm_chip *chip)
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return container_of(chip, struct atmel_hlcdc_pwm, chip);
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}
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static int atmel_hlcdc_pwm_config(struct pwm_chip *c,
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struct pwm_device *pwm,
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int duty_ns, int period_ns)
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static int atmel_hlcdc_pwm_apply(struct pwm_chip *c, struct pwm_device *pwm,
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struct pwm_state *state)
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{
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struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
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struct atmel_hlcdc *hlcdc = chip->hlcdc;
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struct clk *new_clk = hlcdc->slow_clk;
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u64 pwmcval = duty_ns * 256;
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unsigned long clk_freq;
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u64 clk_period_ns;
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u32 pwmcfg;
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int pres;
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unsigned int status;
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int ret;
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if (!chip->errata || !chip->errata->slow_clk_erratum) {
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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if (state->enabled) {
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struct clk *new_clk = hlcdc->slow_clk;
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u64 pwmcval = state->duty_cycle * 256;
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unsigned long clk_freq;
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u64 clk_period_ns;
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u32 pwmcfg;
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int pres;
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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if (!chip->errata || !chip->errata->slow_clk_erratum) {
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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/* Errata: cannot use slow clk on some IP revisions */
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if ((chip->errata && chip->errata->slow_clk_erratum) ||
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clk_period_ns > period_ns) {
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new_clk = hlcdc->sys_clk;
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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/* Errata: cannot use slow clk on some IP revisions */
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if ((chip->errata && chip->errata->slow_clk_erratum) ||
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clk_period_ns > state->period) {
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new_clk = hlcdc->sys_clk;
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clk_freq = clk_get_rate(new_clk);
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if (!clk_freq)
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return -EINVAL;
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for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
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clk_period_ns = (u64)NSEC_PER_SEC * 256;
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do_div(clk_period_ns, clk_freq);
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}
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for (pres = 0; pres <= ATMEL_HLCDC_PWMPS_MAX; pres++) {
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/* Errata: cannot divide by 1 on some IP revisions */
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if (!pres && chip->errata && chip->errata->div1_clk_erratum)
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continue;
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if (!pres && chip->errata &&
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chip->errata->div1_clk_erratum)
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continue;
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if ((clk_period_ns << pres) >= period_ns)
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break;
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}
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if ((clk_period_ns << pres) >= state->period)
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break;
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}
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if (pres > ATMEL_HLCDC_PWMPS_MAX)
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return -EINVAL;
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if (pres > ATMEL_HLCDC_PWMPS_MAX)
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return -EINVAL;
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pwmcfg = ATMEL_HLCDC_PWMPS(pres);
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pwmcfg = ATMEL_HLCDC_PWMPS(pres);
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if (new_clk != chip->cur_clk) {
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u32 gencfg = 0;
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int ret;
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if (new_clk != chip->cur_clk) {
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u32 gencfg = 0;
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int ret;
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ret = clk_prepare_enable(new_clk);
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ret = clk_prepare_enable(new_clk);
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if (ret)
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return ret;
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clk_disable_unprepare(chip->cur_clk);
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chip->cur_clk = new_clk;
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if (new_clk == hlcdc->sys_clk)
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gencfg = ATMEL_HLCDC_CLKPWMSEL;
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ret = regmap_update_bits(hlcdc->regmap,
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ATMEL_HLCDC_CFG(0),
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ATMEL_HLCDC_CLKPWMSEL,
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gencfg);
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if (ret)
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return ret;
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}
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do_div(pwmcval, state->period);
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/*
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* The PWM duty cycle is configurable from 0/256 to 255/256 of
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* the period cycle. Hence we can't set a duty cycle occupying
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* the whole period cycle if we're asked to.
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* Set it to 255 if pwmcval is greater than 256.
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*/
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if (pwmcval > 255)
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pwmcval = 255;
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pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
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if (state->polarity == PWM_POLARITY_NORMAL)
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pwmcfg |= ATMEL_HLCDC_PWMPOL;
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ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
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ATMEL_HLCDC_PWMCVAL_MASK |
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ATMEL_HLCDC_PWMPS_MASK |
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ATMEL_HLCDC_PWMPOL,
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pwmcfg);
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if (ret)
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return ret;
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ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN,
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ATMEL_HLCDC_PWM);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
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status,
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status & ATMEL_HLCDC_PWM,
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10, 0);
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if (ret)
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return ret;
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} else {
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ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS,
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ATMEL_HLCDC_PWM);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(hlcdc->regmap, ATMEL_HLCDC_SR,
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status,
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!(status & ATMEL_HLCDC_PWM),
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10, 0);
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if (ret)
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return ret;
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clk_disable_unprepare(chip->cur_clk);
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chip->cur_clk = new_clk;
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if (new_clk == hlcdc->sys_clk)
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gencfg = ATMEL_HLCDC_CLKPWMSEL;
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ret = regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(0),
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ATMEL_HLCDC_CLKPWMSEL, gencfg);
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if (ret)
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return ret;
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}
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do_div(pwmcval, period_ns);
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/*
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* The PWM duty cycle is configurable from 0/256 to 255/256 of the
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* period cycle. Hence we can't set a duty cycle occupying the
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* whole period cycle if we're asked to.
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* Set it to 255 if pwmcval is greater than 256.
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*/
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if (pwmcval > 255)
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pwmcval = 255;
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pwmcfg |= ATMEL_HLCDC_PWMCVAL(pwmcval);
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return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
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ATMEL_HLCDC_PWMCVAL_MASK |
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ATMEL_HLCDC_PWMPS_MASK,
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pwmcfg);
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}
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static int atmel_hlcdc_pwm_set_polarity(struct pwm_chip *c,
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struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
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struct atmel_hlcdc *hlcdc = chip->hlcdc;
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u32 cfg = 0;
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if (polarity == PWM_POLARITY_NORMAL)
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cfg = ATMEL_HLCDC_PWMPOL;
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return regmap_update_bits(hlcdc->regmap, ATMEL_HLCDC_CFG(6),
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ATMEL_HLCDC_PWMPOL, cfg);
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}
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static int atmel_hlcdc_pwm_enable(struct pwm_chip *c, struct pwm_device *pwm)
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{
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struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
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struct atmel_hlcdc *hlcdc = chip->hlcdc;
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u32 status;
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int ret;
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ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PWM);
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if (ret)
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return ret;
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while (true) {
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ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
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if (ret)
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return ret;
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if ((status & ATMEL_HLCDC_PWM) != 0)
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break;
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usleep_range(1, 10);
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chip->cur_clk = NULL;
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}
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return 0;
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}
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static void atmel_hlcdc_pwm_disable(struct pwm_chip *c,
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struct pwm_device *pwm)
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{
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struct atmel_hlcdc_pwm *chip = to_atmel_hlcdc_pwm(c);
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struct atmel_hlcdc *hlcdc = chip->hlcdc;
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u32 status;
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int ret;
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ret = regmap_write(hlcdc->regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PWM);
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if (ret)
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return;
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while (true) {
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ret = regmap_read(hlcdc->regmap, ATMEL_HLCDC_SR, &status);
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if (ret)
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return;
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if ((status & ATMEL_HLCDC_PWM) == 0)
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break;
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usleep_range(1, 10);
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}
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}
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static const struct pwm_ops atmel_hlcdc_pwm_ops = {
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.config = atmel_hlcdc_pwm_config,
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.set_polarity = atmel_hlcdc_pwm_set_polarity,
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.enable = atmel_hlcdc_pwm_enable,
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.disable = atmel_hlcdc_pwm_disable,
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.apply = atmel_hlcdc_pwm_apply,
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.owner = THIS_MODULE,
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};
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