Two bugfix patches.
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22fbc037cd
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@ -31,7 +31,14 @@ static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu,
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isb();
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}
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/*
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* __load_guest_stage2() includes an ISB only when the AT
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* workaround is applied. Take care of the opposite condition,
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* ensuring that we always have an ISB, but not two ISBs back
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* to back.
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*/
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__load_guest_stage2(mmu);
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asm(ALTERNATIVE("isb", "nop", ARM64_WORKAROUND_SPECULATIVE_AT));
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}
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static void __tlb_switch_to_host(struct tlb_inv_context *cxt)
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@ -794,6 +794,18 @@ void update_exception_bitmap(struct kvm_vcpu *vcpu)
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*/
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if (is_guest_mode(vcpu))
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eb |= get_vmcs12(vcpu)->exception_bitmap;
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else {
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/*
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* If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched
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* between guest and host. In that case we only care about present
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* faults. For vmcs02, however, PFEC_MASK and PFEC_MATCH are set in
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* prepare_vmcs02_rare.
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*/
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bool selective_pf_trap = enable_ept && (eb & (1u << PF_VECTOR));
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int mask = selective_pf_trap ? PFERR_PRESENT_MASK : 0;
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vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, mask);
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vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, mask);
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}
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vmcs_write32(EXCEPTION_BITMAP, eb);
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}
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@ -4355,16 +4367,6 @@ static void init_vmcs(struct vcpu_vmx *vmx)
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vmx->pt_desc.guest.output_mask = 0x7F;
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vmcs_write64(GUEST_IA32_RTIT_CTL, 0);
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}
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/*
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* If EPT is enabled, #PF is only trapped if MAXPHYADDR is mismatched
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* between guest and host. In that case we only care about present
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* faults.
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*/
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if (enable_ept) {
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vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, PFERR_PRESENT_MASK);
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vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, PFERR_PRESENT_MASK);
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}
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}
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static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
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