memstick: fix setup for JMicron 38x controllers
This patch corrects the definition of clock values for JMicron 38x controllers and sets the value properly per interface type. Also, it adds a check for TPC errors in the interrupt handler. Signed-off-by: Aries Lee <arieslee@jmicron.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Cc: Alex Dubov <oakad@yahoo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -61,6 +61,7 @@ struct jmb38x_ms_host {
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struct memstick_request *req;
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unsigned char cmd_flags;
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unsigned char io_pos;
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unsigned char ifmode;
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unsigned int io_word[2];
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};
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@ -136,15 +137,14 @@ struct jmb38x_ms {
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#define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
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#define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
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#define CLOCK_CONTROL_BY_MMIO 0x00000008
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#define CLOCK_CONTROL_40MHZ 0x00000001
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#define CLOCK_CONTROL_50MHZ 0x0000000a
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#define CLOCK_CONTROL_60MHZ 0x00000008
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#define CLOCK_CONTROL_62_5MHZ 0x0000000c
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#define CLOCK_CONTROL_50MHZ 0x00000002
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#define CLOCK_CONTROL_60MHZ 0x00000010
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#define CLOCK_CONTROL_62_5MHZ 0x00000004
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#define CLOCK_CONTROL_OFF 0x00000000
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#define PCI_CTL_CLOCK_DLY_ADDR 0x000000b0
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#define PCI_CTL_CLOCK_DLY_MASK_A 0x00000f00
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#define PCI_CTL_CLOCK_DLY_MASK_B 0x0000f000
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enum {
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CMD_READY = 0x01,
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@ -390,8 +390,13 @@ static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
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if (host->req->data_dir == READ)
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cmd |= TPC_DIR;
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if (host->req->need_card_int)
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cmd |= TPC_WAIT_INT;
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if (host->req->need_card_int) {
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if (host->ifmode == MEMSTICK_SERIAL)
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cmd |= TPC_GET_INT;
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else
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cmd |= TPC_WAIT_INT;
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}
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data = host->req->data;
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@ -529,7 +534,10 @@ static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
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if (irq_status & INT_STATUS_ANY_ERR) {
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if (irq_status & INT_STATUS_CRC_ERR)
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host->req->error = -EILSEQ;
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else
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else if (irq_status & INT_STATUS_TPC_ERR) {
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dev_dbg(&host->chip->pdev->dev, "TPC_ERR\n");
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jmb38x_ms_complete_cmd(msh, 0);
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} else
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host->req->error = -ETIME;
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} else {
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if (host->cmd_flags & DMA_DATA) {
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@ -644,7 +652,6 @@ static int jmb38x_ms_reset(struct jmb38x_ms_host *host)
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ndelay(20);
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}
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dev_dbg(&host->chip->pdev->dev, "reset_req timeout\n");
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/* return -EIO; */
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reset_next:
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writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN
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@ -675,7 +682,7 @@ static int jmb38x_ms_set_param(struct memstick_host *msh,
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{
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struct jmb38x_ms_host *host = memstick_priv(msh);
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unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
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unsigned int clock_ctl = CLOCK_CONTROL_40MHZ, clock_delay = 0;
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unsigned int clock_ctl = CLOCK_CONTROL_BY_MMIO, clock_delay = 0;
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int rc = 0;
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switch (param) {
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@ -687,9 +694,7 @@ static int jmb38x_ms_set_param(struct memstick_host *msh,
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host_ctl = 7;
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host_ctl |= HOST_CONTROL_POWER_EN
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| HOST_CONTROL_CLOCK_EN
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| HOST_CONTROL_HW_OC_P
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| HOST_CONTROL_TDELAY_EN;
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| HOST_CONTROL_CLOCK_EN;
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writel(host_ctl, host->addr + HOST_CONTROL);
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writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
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@ -712,41 +717,42 @@ static int jmb38x_ms_set_param(struct memstick_host *msh,
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return -EINVAL;
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break;
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case MEMSTICK_INTERFACE:
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dev_dbg(&host->chip->pdev->dev,
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"Set Host Interface Mode to %d\n", value);
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host_ctl &= ~(HOST_CONTROL_FAST_CLK | HOST_CONTROL_REI |
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HOST_CONTROL_REO);
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host_ctl |= HOST_CONTROL_TDELAY_EN | HOST_CONTROL_HW_OC_P;
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host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
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pci_read_config_dword(host->chip->pdev,
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PCI_CTL_CLOCK_DLY_ADDR,
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&clock_delay);
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clock_delay &= host->id ? ~PCI_CTL_CLOCK_DLY_MASK_B
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: ~PCI_CTL_CLOCK_DLY_MASK_A;
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if (value == MEMSTICK_SERIAL) {
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host_ctl &= ~HOST_CONTROL_FAST_CLK;
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host_ctl &= ~HOST_CONTROL_REO;
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host_ctl |= HOST_CONTROL_IF_SERIAL
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<< HOST_CONTROL_IF_SHIFT;
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host_ctl |= HOST_CONTROL_REI;
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clock_ctl = CLOCK_CONTROL_40MHZ;
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clock_ctl |= CLOCK_CONTROL_40MHZ;
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clock_delay = 0;
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} else if (value == MEMSTICK_PAR4) {
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host_ctl |= HOST_CONTROL_FAST_CLK | HOST_CONTROL_REO;
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host_ctl |= HOST_CONTROL_FAST_CLK;
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host_ctl |= HOST_CONTROL_IF_PAR4
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<< HOST_CONTROL_IF_SHIFT;
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host_ctl &= ~HOST_CONTROL_REI;
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clock_ctl = CLOCK_CONTROL_40MHZ;
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clock_delay |= host->id ? (4 << 12) : (4 << 8);
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host_ctl |= HOST_CONTROL_REO;
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clock_ctl |= CLOCK_CONTROL_40MHZ;
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clock_delay = 4;
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} else if (value == MEMSTICK_PAR8) {
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host_ctl |= HOST_CONTROL_FAST_CLK;
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host_ctl |= HOST_CONTROL_IF_PAR8
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<< HOST_CONTROL_IF_SHIFT;
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host_ctl &= ~(HOST_CONTROL_REI | HOST_CONTROL_REO);
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clock_ctl = CLOCK_CONTROL_50MHZ;
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clock_ctl |= CLOCK_CONTROL_50MHZ;
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clock_delay = 0;
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} else
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return -EINVAL;
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writel(host_ctl, host->addr + HOST_CONTROL);
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writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL);
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writel(clock_ctl, host->addr + CLOCK_CONTROL);
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pci_write_config_dword(host->chip->pdev,
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PCI_CTL_CLOCK_DLY_ADDR,
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clock_delay);
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pci_write_config_byte(host->chip->pdev,
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PCI_CTL_CLOCK_DLY_ADDR + 1,
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clock_delay);
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host->ifmode = value;
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break;
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};
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return 0;
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