bnx2x: Supporting Device Control Channel
In multi-function mode, the FW can receive special management control commands to set the Min/Max BW and the the function link state Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
a1d58179d1
commit
2691d51d72
@ -128,6 +128,11 @@
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#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
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#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
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#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
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offsetof(struct shmem2_region, field))
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#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
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#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
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#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
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#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
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@ -535,6 +540,7 @@ struct bnx2x_common {
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#define NVRAM_PAGE_SIZE 256
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u32 shmem_base;
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u32 shmem2_base;
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u32 hw_config;
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@ -658,6 +658,8 @@ struct drv_func_mb {
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#define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
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#define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
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#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
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#define DRV_MSG_CODE_DCC_OK 0x30000000
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#define DRV_MSG_CODE_DCC_FAILURE 0x31000000
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#define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
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#define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
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#define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
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@ -692,6 +694,7 @@ struct drv_func_mb {
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#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
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#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
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#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
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#define FW_MSG_CODE_DCC_DONE 0x30100000
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#define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
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#define FW_MSG_CODE_DIAG_REFUSE 0x50200000
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#define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
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@ -742,6 +745,14 @@ struct drv_func_mb {
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u32 drv_status;
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#define DRV_STATUS_PMF 0x00000001
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#define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
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#define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
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#define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
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#define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
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#define DRV_STATUS_DCC_RESERVED1 0x00000800
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#define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
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#define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
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u32 virt_mac_upper;
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#define VIRT_MAC_SIGN_MASK 0xffff0000
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#define VIRT_MAC_SIGNATURE 0x564d0000
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@ -778,10 +789,9 @@ struct shared_mf_cfg {
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struct port_mf_cfg {
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u32 dynamic_cfg; /* device control channel */
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#define PORT_MF_CFG_OUTER_VLAN_TAG_MASK 0x0000ffff
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#define PORT_MF_CFG_OUTER_VLAN_TAG_SHIFT 0
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#define PORT_MF_CFG_DYNAMIC_CFG_ENABLED 0x00010000
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#define PORT_MF_CFG_DYNAMIC_CFG_DEFAULT 0x00000000
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#define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
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#define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
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#define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
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u32 reserved[3];
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@ -885,6 +895,22 @@ struct shmem_region { /* SharedMem Offset (size) */
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}; /* 0x6dc */
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struct shmem2_region {
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u32 size;
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u32 dcc_support;
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#define SHMEM_DCC_SUPPORT_NONE 0x00000000
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#define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
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#define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
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#define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
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#define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
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#define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
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#define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
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};
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struct emac_stats {
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u32 rx_stat_ifhcinoctets;
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u32 rx_stat_ifhcinbadoctets;
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@ -2104,6 +2104,12 @@ static void bnx2x_calc_fc_adv(struct bnx2x *bp)
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static void bnx2x_link_report(struct bnx2x *bp)
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{
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if (bp->state == BNX2X_STATE_DISABLED) {
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netif_carrier_off(bp->dev);
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printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
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return;
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}
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if (bp->link_vars.link_up) {
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if (bp->state == BNX2X_STATE_OPEN)
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netif_carrier_on(bp->dev);
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@ -2240,6 +2246,46 @@ static void bnx2x_init_port_minmax(struct bnx2x *bp)
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bp->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
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}
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/* Calculates the sum of vn_min_rates.
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It's needed for further normalizing of the min_rates.
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Returns:
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sum of vn_min_rates.
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or
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0 - if all the min_rates are 0.
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In the later case fainess algorithm should be deactivated.
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If not all min_rates are zero then those that are zeroes will be set to 1.
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*/
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static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
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{
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int all_zero = 1;
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int port = BP_PORT(bp);
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int vn;
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bp->vn_weight_sum = 0;
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for (vn = VN_0; vn < E1HVN_MAX; vn++) {
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int func = 2*vn + port;
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u32 vn_cfg = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
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u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
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FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
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/* Skip hidden vns */
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if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
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continue;
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/* If min rate is zero - set it to 1 */
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if (!vn_min_rate)
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vn_min_rate = DEF_MIN_RATE;
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else
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all_zero = 0;
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bp->vn_weight_sum += vn_min_rate;
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}
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/* ... only if all min rates are zeros - disable fairness */
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if (all_zero)
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bp->vn_weight_sum = 0;
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}
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static void bnx2x_init_vn_minmax(struct bnx2x *bp, int func)
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{
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struct rate_shaping_vars_per_vn m_rs_vn;
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@ -2383,6 +2429,8 @@ static void bnx2x_link_attn(struct bnx2x *bp)
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static void bnx2x__link_status_update(struct bnx2x *bp)
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{
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int func = BP_FUNC(bp);
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if (bp->state != BNX2X_STATE_OPEN)
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return;
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@ -2393,6 +2441,9 @@ static void bnx2x__link_status_update(struct bnx2x *bp)
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else
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bnx2x_stats_handle(bp, STATS_EVENT_STOP);
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bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
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bnx2x_calc_vn_weight_sum(bp);
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/* indicate link status */
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bnx2x_link_report(bp);
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}
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@ -2421,6 +2472,152 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
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* General service functions
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*/
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/* send the MCP a request, block until there is a reply */
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u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
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{
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int func = BP_FUNC(bp);
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u32 seq = ++bp->fw_seq;
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u32 rc = 0;
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u32 cnt = 1;
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u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
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SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
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DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
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do {
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/* let the FW do it's magic ... */
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msleep(delay);
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rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
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/* Give the FW up to 2 second (200*10ms) */
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} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
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DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
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cnt*delay, rc, seq);
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/* is this a reply to our command? */
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if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
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rc &= FW_MSG_CODE_MASK;
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else {
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/* FW BUG! */
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BNX2X_ERR("FW failed to respond!\n");
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bnx2x_fw_dump(bp);
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rc = 0;
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}
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return rc;
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}
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static void bnx2x_set_storm_rx_mode(struct bnx2x *bp);
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static void bnx2x_set_mac_addr_e1h(struct bnx2x *bp, int set);
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static void bnx2x_set_rx_mode(struct net_device *dev);
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static void bnx2x_e1h_disable(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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int i;
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bp->rx_mode = BNX2X_RX_MODE_NONE;
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bnx2x_set_storm_rx_mode(bp);
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netif_tx_disable(bp->dev);
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bp->dev->trans_start = jiffies; /* prevent tx timeout */
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REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
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bnx2x_set_mac_addr_e1h(bp, 0);
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for (i = 0; i < MC_HASH_SIZE; i++)
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REG_WR(bp, MC_HASH_OFFSET(bp, i), 0);
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netif_carrier_off(bp->dev);
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}
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static void bnx2x_e1h_enable(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
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bnx2x_set_mac_addr_e1h(bp, 1);
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/* Tx queue should be only reenabled */
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netif_tx_wake_all_queues(bp->dev);
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/* Initialize the receive filter. */
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bnx2x_set_rx_mode(bp->dev);
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}
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static void bnx2x_update_min_max(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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int vn, i;
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/* Init rate shaping and fairness contexts */
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bnx2x_init_port_minmax(bp);
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bnx2x_calc_vn_weight_sum(bp);
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for (vn = VN_0; vn < E1HVN_MAX; vn++)
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bnx2x_init_vn_minmax(bp, 2*vn + port);
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if (bp->port.pmf) {
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int func;
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/* Set the attention towards other drivers on the same port */
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for (vn = VN_0; vn < E1HVN_MAX; vn++) {
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if (vn == BP_E1HVN(bp))
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continue;
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func = ((vn << 1) | port);
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REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
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(LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
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}
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/* Store it to internal memory */
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for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
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REG_WR(bp, BAR_XSTRORM_INTMEM +
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XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
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((u32 *)(&bp->cmng))[i]);
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}
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}
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static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
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{
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int func = BP_FUNC(bp);
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DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
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bp->mf_config = SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
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if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
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if (bp->mf_config & FUNC_MF_CFG_FUNC_DISABLED) {
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DP(NETIF_MSG_IFDOWN, "mf_cfg function disabled\n");
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bp->state = BNX2X_STATE_DISABLED;
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bnx2x_e1h_disable(bp);
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} else {
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DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
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bp->state = BNX2X_STATE_OPEN;
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bnx2x_e1h_enable(bp);
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}
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dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
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}
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if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
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bnx2x_update_min_max(bp);
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dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
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}
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/* Report results to MCP */
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if (dcc_event)
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bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE);
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else
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bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK);
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}
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/* the slow path queue is odd since completions arrive on the fastpath ring */
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static int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
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u32 data_hi, u32 data_lo, int common)
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@ -2806,9 +3003,12 @@ static inline void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
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int func = BP_FUNC(bp);
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REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
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val = SHMEM_RD(bp, func_mb[func].drv_status);
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if (val & DRV_STATUS_DCC_EVENT_MASK)
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bnx2x_dcc_event(bp,
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(val & DRV_STATUS_DCC_EVENT_MASK));
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bnx2x__link_status_update(bp);
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if (SHMEM_RD(bp, func_mb[func].drv_status) &
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DRV_STATUS_PMF)
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if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
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bnx2x_pmf_update(bp);
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} else if (attn & BNX2X_MC_ASSERT_BITS) {
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@ -4968,47 +5168,6 @@ static void bnx2x_init_internal_port(struct bnx2x *bp)
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REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BNX2X_BTR);
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}
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/* Calculates the sum of vn_min_rates.
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It's needed for further normalizing of the min_rates.
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Returns:
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sum of vn_min_rates.
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or
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0 - if all the min_rates are 0.
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In the later case fainess algorithm should be deactivated.
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If not all min_rates are zero then those that are zeroes will be set to 1.
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*/
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static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
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{
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int all_zero = 1;
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int port = BP_PORT(bp);
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int vn;
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bp->vn_weight_sum = 0;
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for (vn = VN_0; vn < E1HVN_MAX; vn++) {
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int func = 2*vn + port;
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u32 vn_cfg =
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SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
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u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
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FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
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/* Skip hidden vns */
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if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
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continue;
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/* If min rate is zero - set it to 1 */
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if (!vn_min_rate)
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vn_min_rate = DEF_MIN_RATE;
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else
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all_zero = 0;
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bp->vn_weight_sum += vn_min_rate;
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}
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/* ... only if all min rates are zeros - disable fairness */
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if (all_zero)
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bp->vn_weight_sum = 0;
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}
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static void bnx2x_init_internal_func(struct bnx2x *bp)
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{
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struct tstorm_eth_function_common_config tstorm_config = {0};
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@ -6272,44 +6431,6 @@ static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
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return rc;
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}
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/* send the MCP a request, block until there is a reply */
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u32 bnx2x_fw_command(struct bnx2x *bp, u32 command)
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{
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int func = BP_FUNC(bp);
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u32 seq = ++bp->fw_seq;
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u32 rc = 0;
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u32 cnt = 1;
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u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
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SHMEM_WR(bp, func_mb[func].drv_mb_header, (command | seq));
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DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB\n", (command | seq));
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do {
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/* let the FW do it's magic ... */
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msleep(delay);
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rc = SHMEM_RD(bp, func_mb[func].fw_mb_header);
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/* Give the FW up to 2 second (200*10ms) */
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} while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 200));
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DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
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cnt*delay, rc, seq);
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/* is this a reply to our command? */
|
||||
if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) {
|
||||
rc &= FW_MSG_CODE_MASK;
|
||||
|
||||
} else {
|
||||
/* FW BUG! */
|
||||
BNX2X_ERR("FW failed to respond!\n");
|
||||
bnx2x_fw_dump(bp);
|
||||
rc = 0;
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void bnx2x_free_mem(struct bnx2x *bp)
|
||||
{
|
||||
|
||||
@ -6996,7 +7117,6 @@ static int bnx2x_set_int_mode(struct bnx2x *bp)
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void bnx2x_set_rx_mode(struct net_device *dev);
|
||||
|
||||
/* must be called with rtnl_lock */
|
||||
static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||
@ -7103,6 +7223,12 @@ static int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
|
||||
/* Setup NIC internals and enable interrupts */
|
||||
bnx2x_nic_init(bp, load_code);
|
||||
|
||||
if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
|
||||
(bp->common.shmem2_base))
|
||||
SHMEM2_WR(bp, dcc_support,
|
||||
(SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
|
||||
SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
|
||||
|
||||
/* Send LOAD_DONE command to MCP */
|
||||
if (!BP_NOMCP(bp)) {
|
||||
load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE);
|
||||
@ -7735,8 +7861,10 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
|
||||
bp->common.flash_size, bp->common.flash_size);
|
||||
|
||||
bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
|
||||
bp->common.shmem2_base = REG_RD(bp, MISC_REG_GENERIC_CR_0);
|
||||
bp->link_params.shmem_base = bp->common.shmem_base;
|
||||
BNX2X_DEV_INFO("shmem offset is 0x%x\n", bp->common.shmem_base);
|
||||
BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
|
||||
bp->common.shmem_base, bp->common.shmem2_base);
|
||||
|
||||
if (!bp->common.shmem_base ||
|
||||
(bp->common.shmem_base < 0xA0000) ||
|
||||
@ -8290,22 +8418,33 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
|
||||
bp->mf_config =
|
||||
SHMEM_RD(bp, mf_cfg.func_mf_config[func].config);
|
||||
|
||||
val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].e1hov_tag) &
|
||||
val = (SHMEM_RD(bp, mf_cfg.func_mf_config[FUNC_0].e1hov_tag) &
|
||||
FUNC_MF_CFG_E1HOV_TAG_MASK);
|
||||
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
|
||||
|
||||
bp->e1hov = val;
|
||||
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
|
||||
bp->e1hmf = 1;
|
||||
BNX2X_DEV_INFO("MF mode E1HOV for func %d is %d "
|
||||
"(0x%04x)\n",
|
||||
func, bp->e1hov, bp->e1hov);
|
||||
} else {
|
||||
BNX2X_DEV_INFO("single function mode\n");
|
||||
if (BP_E1HVN(bp)) {
|
||||
BNX2X_DEV_INFO("%s function mode\n",
|
||||
IS_E1HMF(bp) ? "multi" : "single");
|
||||
|
||||
if (IS_E1HMF(bp)) {
|
||||
val = (SHMEM_RD(bp, mf_cfg.func_mf_config[func].
|
||||
e1hov_tag) &
|
||||
FUNC_MF_CFG_E1HOV_TAG_MASK);
|
||||
if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
|
||||
bp->e1hov = val;
|
||||
BNX2X_DEV_INFO("E1HOV for func %d is %d "
|
||||
"(0x%04x)\n",
|
||||
func, bp->e1hov, bp->e1hov);
|
||||
} else {
|
||||
BNX2X_ERR("!!! No valid E1HOV for func %d,"
|
||||
" aborting\n", func);
|
||||
rc = -EPERM;
|
||||
}
|
||||
} else {
|
||||
if (BP_E1HVN(bp)) {
|
||||
BNX2X_ERR("!!! VN %d in single function mode,"
|
||||
" aborting\n", BP_E1HVN(bp));
|
||||
rc = -EPERM;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user