i2c-pnx.c: Remove duplicated i2c.h
The platforms using i2c-pnx.c both defined a duplicated i2c.h (used nowhere else). This patch removes those and integrates the contents into the driver itself. Signed-off-by: Roland Stigge <stigge@antcom.de> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
This commit is contained in:
Roland Stigge
Wolfram Sang
parent
77701a8bab
commit
26f8d43df7
@ -1,63 +0,0 @@
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/*
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* PNX4008-specific tweaks for I2C IP3204 block
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*
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* Author: Vitaly Wool <vwool@ru.mvista.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_I2C_H
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#define __ASM_ARCH_I2C_H
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enum {
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mstatus_tdi = 0x00000001,
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mstatus_afi = 0x00000002,
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mstatus_nai = 0x00000004,
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mstatus_drmi = 0x00000008,
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mstatus_active = 0x00000020,
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mstatus_scl = 0x00000040,
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mstatus_sda = 0x00000080,
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mstatus_rff = 0x00000100,
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mstatus_rfe = 0x00000200,
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mstatus_tff = 0x00000400,
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mstatus_tfe = 0x00000800,
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};
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enum {
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mcntrl_tdie = 0x00000001,
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mcntrl_afie = 0x00000002,
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mcntrl_naie = 0x00000004,
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mcntrl_drmie = 0x00000008,
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mcntrl_daie = 0x00000020,
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mcntrl_rffie = 0x00000040,
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mcntrl_tffie = 0x00000080,
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mcntrl_reset = 0x00000100,
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mcntrl_cdbmode = 0x00000400,
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};
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enum {
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rw_bit = 1 << 0,
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start_bit = 1 << 8,
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stop_bit = 1 << 9,
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};
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#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
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#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
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#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
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#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
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#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
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#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
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#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
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#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
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#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
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#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
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#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
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#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
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#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
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#define I2C_CHIP_NAME "PNX4008-I2C"
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#endif /* __ASM_ARCH_I2C_H */
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@ -1,64 +0,0 @@
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/*
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* PNX4008-specific tweaks for I2C IP3204 block
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*
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* Author: Vitaly Wool <vwool@ru.mvista.com>
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_I2C_H__
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#define __ASM_ARCH_I2C_H__
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enum {
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mstatus_tdi = 0x00000001,
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mstatus_afi = 0x00000002,
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mstatus_nai = 0x00000004,
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mstatus_drmi = 0x00000008,
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mstatus_active = 0x00000020,
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mstatus_scl = 0x00000040,
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mstatus_sda = 0x00000080,
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mstatus_rff = 0x00000100,
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mstatus_rfe = 0x00000200,
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mstatus_tff = 0x00000400,
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mstatus_tfe = 0x00000800,
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};
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enum {
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mcntrl_tdie = 0x00000001,
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mcntrl_afie = 0x00000002,
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mcntrl_naie = 0x00000004,
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mcntrl_drmie = 0x00000008,
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mcntrl_daie = 0x00000020,
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mcntrl_rffie = 0x00000040,
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mcntrl_tffie = 0x00000080,
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mcntrl_reset = 0x00000100,
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mcntrl_cdbmode = 0x00000400,
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};
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enum {
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rw_bit = 1 << 0,
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start_bit = 1 << 8,
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stop_bit = 1 << 9,
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};
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#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
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#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
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#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
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#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
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#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
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#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
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#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
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#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
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#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
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#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
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#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
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#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
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#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
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#define HCLK_MHZ 13
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#define I2C_CHIP_NAME "PNX4008-I2C"
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#endif /* __ASM_ARCH_I2C_H___ */
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@ -24,13 +24,56 @@
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#include <linux/clk.h>
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#include <linux/slab.h>
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#include <mach/hardware.h>
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#include <mach/i2c.h>
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#define I2C_PNX_TIMEOUT 10 /* msec */
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#define I2C_PNX_SPEED_KHZ 100
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#define I2C_PNX_REGION_SIZE 0x100
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enum {
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mstatus_tdi = 0x00000001,
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mstatus_afi = 0x00000002,
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mstatus_nai = 0x00000004,
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mstatus_drmi = 0x00000008,
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mstatus_active = 0x00000020,
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mstatus_scl = 0x00000040,
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mstatus_sda = 0x00000080,
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mstatus_rff = 0x00000100,
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mstatus_rfe = 0x00000200,
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mstatus_tff = 0x00000400,
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mstatus_tfe = 0x00000800,
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};
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enum {
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mcntrl_tdie = 0x00000001,
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mcntrl_afie = 0x00000002,
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mcntrl_naie = 0x00000004,
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mcntrl_drmie = 0x00000008,
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mcntrl_daie = 0x00000020,
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mcntrl_rffie = 0x00000040,
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mcntrl_tffie = 0x00000080,
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mcntrl_reset = 0x00000100,
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mcntrl_cdbmode = 0x00000400,
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};
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enum {
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rw_bit = 1 << 0,
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start_bit = 1 << 8,
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stop_bit = 1 << 9,
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};
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#define I2C_REG_RX(a) ((a)->ioaddr) /* Rx FIFO reg (RO) */
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#define I2C_REG_TX(a) ((a)->ioaddr) /* Tx FIFO reg (WO) */
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#define I2C_REG_STS(a) ((a)->ioaddr + 0x04) /* Status reg (RO) */
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#define I2C_REG_CTL(a) ((a)->ioaddr + 0x08) /* Ctl reg */
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#define I2C_REG_CKL(a) ((a)->ioaddr + 0x0c) /* Clock divider low */
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#define I2C_REG_CKH(a) ((a)->ioaddr + 0x10) /* Clock divider high */
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#define I2C_REG_ADR(a) ((a)->ioaddr + 0x14) /* I2C address */
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#define I2C_REG_RFL(a) ((a)->ioaddr + 0x18) /* Rx FIFO level (RO) */
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#define I2C_REG_TFL(a) ((a)->ioaddr + 0x1c) /* Tx FIFO level (RO) */
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#define I2C_REG_RXB(a) ((a)->ioaddr + 0x20) /* Num of bytes Rx-ed (RO) */
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#define I2C_REG_TXB(a) ((a)->ioaddr + 0x24) /* Num of bytes Tx-ed (RO) */
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#define I2C_REG_TXS(a) ((a)->ioaddr + 0x28) /* Tx slave FIFO (RO) */
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#define I2C_REG_STFL(a) ((a)->ioaddr + 0x2c) /* Tx slave FIFO level (RO) */
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static inline int wait_timeout(long timeout, struct i2c_pnx_algo_data *data)
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{
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while (timeout > 0 &&
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