PM / devfreq: exynos-ppmu: Use the regmap interface to handle the registers
This patch uses the regmap interface to read and write the registers for exynos PPMU device instead of the legacy memory map functions. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
This commit is contained in:
Chanwoo Choi
MyungJoo Ham
parent
b513652443
commit
2a3ea64789
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@ -17,13 +17,13 @@
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/suspend.h>
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#include <linux/devfreq-event.h>
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#include "exynos-ppmu.h"
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struct exynos_ppmu_data {
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void __iomem *base;
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struct clk *clk;
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};
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@ -33,6 +33,7 @@ struct exynos_ppmu {
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unsigned int num_events;
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struct device *dev;
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struct regmap *regmap;
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struct exynos_ppmu_data ppmu;
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};
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@ -107,20 +108,28 @@ static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev)
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static int exynos_ppmu_disable(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int ret;
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u32 pmnc;
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/* Disable all counters */
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__raw_writel(PPMU_CCNT_MASK |
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PPMU_PMCNT0_MASK |
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PPMU_PMCNT1_MASK |
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PPMU_PMCNT2_MASK |
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PPMU_PMCNT3_MASK,
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info->ppmu.base + PPMU_CNTENC);
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ret = regmap_write(info->regmap, PPMU_CNTENC,
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PPMU_CCNT_MASK |
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PPMU_PMCNT0_MASK |
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PPMU_PMCNT1_MASK |
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PPMU_PMCNT2_MASK |
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PPMU_PMCNT3_MASK);
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if (ret < 0)
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return ret;
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/* Disable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC);
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ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc);
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if (ret < 0)
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return ret;
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pmnc &= ~PPMU_PMNC_ENABLE_MASK;
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__raw_writel(pmnc, info->ppmu.base + PPMU_PMNC);
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ret = regmap_write(info->regmap, PPMU_PMNC, pmnc);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -129,29 +138,42 @@ static int exynos_ppmu_set_event(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int id = exynos_ppmu_find_ppmu_id(edev);
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int ret;
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u32 pmnc, cntens;
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if (id < 0)
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return id;
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/* Enable specific counter */
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cntens = __raw_readl(info->ppmu.base + PPMU_CNTENS);
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ret = regmap_read(info->regmap, PPMU_CNTENS, &cntens);
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if (ret < 0)
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return ret;
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cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id));
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__raw_writel(cntens, info->ppmu.base + PPMU_CNTENS);
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ret = regmap_write(info->regmap, PPMU_CNTENS, cntens);
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if (ret < 0)
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return ret;
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/* Set the event of Read/Write data count */
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__raw_writel(PPMU_RO_DATA_CNT | PPMU_WO_DATA_CNT,
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info->ppmu.base + PPMU_BEVTxSEL(id));
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ret = regmap_write(info->regmap, PPMU_BEVTxSEL(id),
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PPMU_RO_DATA_CNT | PPMU_WO_DATA_CNT);
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if (ret < 0)
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return ret;
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/* Reset cycle counter/performance counter and enable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC);
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ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc);
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if (ret < 0)
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return ret;
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pmnc &= ~(PPMU_PMNC_ENABLE_MASK
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| PPMU_PMNC_COUNTER_RESET_MASK
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| PPMU_PMNC_CC_RESET_MASK);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_ENABLE_SHIFT);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT);
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__raw_writel(pmnc, info->ppmu.base + PPMU_PMNC);
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ret = regmap_write(info->regmap, PPMU_PMNC, pmnc);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -161,40 +183,64 @@ static int exynos_ppmu_get_event(struct devfreq_event_dev *edev,
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int id = exynos_ppmu_find_ppmu_id(edev);
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u32 pmnc, cntenc;
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unsigned int total_count, load_count;
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unsigned int pmcnt3_high, pmcnt3_low;
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unsigned int pmnc, cntenc;
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int ret;
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if (id < 0)
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return -EINVAL;
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/* Disable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_PMNC);
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ret = regmap_read(info->regmap, PPMU_PMNC, &pmnc);
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if (ret < 0)
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return ret;
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pmnc &= ~PPMU_PMNC_ENABLE_MASK;
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__raw_writel(pmnc, info->ppmu.base + PPMU_PMNC);
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ret = regmap_write(info->regmap, PPMU_PMNC, pmnc);
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if (ret < 0)
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return ret;
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/* Read cycle count */
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edata->total_count = __raw_readl(info->ppmu.base + PPMU_CCNT);
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ret = regmap_read(info->regmap, PPMU_CCNT, &total_count);
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if (ret < 0)
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return ret;
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edata->total_count = total_count;
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/* Read performance count */
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switch (id) {
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case PPMU_PMNCNT0:
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case PPMU_PMNCNT1:
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case PPMU_PMNCNT2:
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edata->load_count
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= __raw_readl(info->ppmu.base + PPMU_PMNCT(id));
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ret = regmap_read(info->regmap, PPMU_PMNCT(id), &load_count);
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if (ret < 0)
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return ret;
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edata->load_count = load_count;
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break;
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case PPMU_PMNCNT3:
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edata->load_count =
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((__raw_readl(info->ppmu.base + PPMU_PMCNT3_HIGH) << 8)
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| __raw_readl(info->ppmu.base + PPMU_PMCNT3_LOW));
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ret = regmap_read(info->regmap, PPMU_PMCNT3_HIGH, &pmcnt3_high);
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if (ret < 0)
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return ret;
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ret = regmap_read(info->regmap, PPMU_PMCNT3_LOW, &pmcnt3_low);
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if (ret < 0)
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return ret;
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edata->load_count = ((pmcnt3_high << 8) | pmcnt3_low);
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break;
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default:
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return -EINVAL;
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}
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/* Disable specific counter */
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cntenc = __raw_readl(info->ppmu.base + PPMU_CNTENC);
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ret = regmap_read(info->regmap, PPMU_CNTENC, &cntenc);
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if (ret < 0)
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return ret;
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cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id));
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__raw_writel(cntenc, info->ppmu.base + PPMU_CNTENC);
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ret = regmap_write(info->regmap, PPMU_CNTENC, cntenc);
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if (ret < 0)
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return ret;
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dev_dbg(&edev->dev, "%s (event: %ld/%ld)\n", edev->desc->name,
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edata->load_count, edata->total_count);
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@ -214,36 +260,93 @@ static const struct devfreq_event_ops exynos_ppmu_ops = {
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static int exynos_ppmu_v2_disable(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int ret;
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u32 pmnc, clear;
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/* Disable all counters */
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clear = (PPMU_CCNT_MASK | PPMU_PMCNT0_MASK | PPMU_PMCNT1_MASK
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| PPMU_PMCNT2_MASK | PPMU_PMCNT3_MASK);
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ret = regmap_write(info->regmap, PPMU_V2_FLAG, clear);
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if (ret < 0)
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return ret;
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__raw_writel(clear, info->ppmu.base + PPMU_V2_FLAG);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_INTENC);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_CNTENC);
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__raw_writel(clear, info->ppmu.base + PPMU_V2_CNT_RESET);
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ret = regmap_write(info->regmap, PPMU_V2_INTENC, clear);
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if (ret < 0)
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return ret;
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG0);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG1);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_CFG2);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CIG_RESULT);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CNT_AUTO);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV0_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV1_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV2_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_CH_EV3_TYPE);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_ID_V);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_ID_A);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_OTHERS_V);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_SM_OTHERS_A);
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__raw_writel(0x0, info->ppmu.base + PPMU_V2_INTERRUPT_RESET);
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ret = regmap_write(info->regmap, PPMU_V2_CNTENC, clear);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CNT_RESET, clear);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG0, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG1, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CIG_CFG2, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CIG_RESULT, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CNT_AUTO, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV0_TYPE, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV1_TYPE, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV2_TYPE, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_CH_EV3_TYPE, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_SM_ID_V, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_SM_ID_A, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_SM_OTHERS_V, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_SM_OTHERS_A, 0x0);
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if (ret < 0)
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return ret;
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ret = regmap_write(info->regmap, PPMU_V2_INTERRUPT_RESET, 0x0);
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if (ret < 0)
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return ret;
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/* Disable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC);
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ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc);
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if (ret < 0)
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return ret;
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pmnc &= ~PPMU_PMNC_ENABLE_MASK;
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__raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC);
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ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -251,30 +354,43 @@ static int exynos_ppmu_v2_disable(struct devfreq_event_dev *edev)
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static int exynos_ppmu_v2_set_event(struct devfreq_event_dev *edev)
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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unsigned int pmnc, cntens;
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int id = exynos_ppmu_find_ppmu_id(edev);
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u32 pmnc, cntens;
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int ret;
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/* Enable all counters */
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cntens = __raw_readl(info->ppmu.base + PPMU_V2_CNTENS);
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ret = regmap_read(info->regmap, PPMU_V2_CNTENS, &cntens);
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if (ret < 0)
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return ret;
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cntens |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id));
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__raw_writel(cntens, info->ppmu.base + PPMU_V2_CNTENS);
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ret = regmap_write(info->regmap, PPMU_V2_CNTENS, cntens);
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if (ret < 0)
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return ret;
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/* Set the event of Read/Write data count */
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switch (id) {
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case PPMU_PMNCNT0:
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case PPMU_PMNCNT1:
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case PPMU_PMNCNT2:
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__raw_writel(PPMU_V2_RO_DATA_CNT | PPMU_V2_WO_DATA_CNT,
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info->ppmu.base + PPMU_V2_CH_EVx_TYPE(id));
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ret = regmap_write(info->regmap, PPMU_V2_CH_EVx_TYPE(id),
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PPMU_V2_RO_DATA_CNT | PPMU_V2_WO_DATA_CNT);
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if (ret < 0)
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return ret;
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break;
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case PPMU_PMNCNT3:
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__raw_writel(PPMU_V2_EVT3_RW_DATA_CNT,
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info->ppmu.base + PPMU_V2_CH_EVx_TYPE(id));
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ret = regmap_write(info->regmap, PPMU_V2_CH_EVx_TYPE(id),
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PPMU_V2_EVT3_RW_DATA_CNT);
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if (ret < 0)
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return ret;
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break;
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}
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/* Reset cycle counter/performance counter and enable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC);
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ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc);
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if (ret < 0)
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return ret;
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pmnc &= ~(PPMU_PMNC_ENABLE_MASK
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| PPMU_PMNC_COUNTER_RESET_MASK
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| PPMU_PMNC_CC_RESET_MASK
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@ -284,7 +400,10 @@ static int exynos_ppmu_v2_set_event(struct devfreq_event_dev *edev)
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_COUNTER_RESET_SHIFT);
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pmnc |= (PPMU_ENABLE << PPMU_PMNC_CC_RESET_SHIFT);
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pmnc |= (PPMU_V2_MODE_MANUAL << PPMU_V2_PMNC_START_MODE_SHIFT);
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__raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC);
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ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc);
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if (ret < 0)
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return ret;
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return 0;
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}
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@ -294,37 +413,61 @@ static int exynos_ppmu_v2_get_event(struct devfreq_event_dev *edev,
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{
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struct exynos_ppmu *info = devfreq_event_get_drvdata(edev);
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int id = exynos_ppmu_find_ppmu_id(edev);
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u32 pmnc, cntenc;
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u32 pmcnt_high, pmcnt_low;
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u64 load_count = 0;
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int ret;
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unsigned int pmnc, cntenc;
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unsigned int pmcnt_high, pmcnt_low;
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unsigned int total_count, count;
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unsigned long load_count = 0;
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/* Disable PPMU */
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pmnc = __raw_readl(info->ppmu.base + PPMU_V2_PMNC);
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ret = regmap_read(info->regmap, PPMU_V2_PMNC, &pmnc);
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if (ret < 0)
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return ret;
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pmnc &= ~PPMU_PMNC_ENABLE_MASK;
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__raw_writel(pmnc, info->ppmu.base + PPMU_V2_PMNC);
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ret = regmap_write(info->regmap, PPMU_V2_PMNC, pmnc);
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if (ret < 0)
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return ret;
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/* Read cycle count and performance count */
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edata->total_count = __raw_readl(info->ppmu.base + PPMU_V2_CCNT);
|
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ret = regmap_read(info->regmap, PPMU_V2_CCNT, &total_count);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
edata->total_count = total_count;
|
||||
|
||||
switch (id) {
|
||||
case PPMU_PMNCNT0:
|
||||
case PPMU_PMNCNT1:
|
||||
case PPMU_PMNCNT2:
|
||||
load_count = __raw_readl(info->ppmu.base + PPMU_V2_PMNCT(id));
|
||||
ret = regmap_read(info->regmap, PPMU_V2_PMNCT(id), &count);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
load_count = count;
|
||||
break;
|
||||
case PPMU_PMNCNT3:
|
||||
pmcnt_high = __raw_readl(info->ppmu.base + PPMU_V2_PMCNT3_HIGH);
|
||||
pmcnt_low = __raw_readl(info->ppmu.base + PPMU_V2_PMCNT3_LOW);
|
||||
load_count = ((u64)((pmcnt_high & 0xff)) << 32)
|
||||
+ (u64)pmcnt_low;
|
||||
ret = regmap_read(info->regmap, PPMU_V2_PMCNT3_HIGH,
|
||||
&pmcnt_high);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = regmap_read(info->regmap, PPMU_V2_PMCNT3_LOW, &pmcnt_low);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
load_count = ((u64)((pmcnt_high & 0xff)) << 32)+ (u64)pmcnt_low;
|
||||
break;
|
||||
}
|
||||
edata->load_count = load_count;
|
||||
|
||||
/* Disable all counters */
|
||||
cntenc = __raw_readl(info->ppmu.base + PPMU_V2_CNTENC);
|
||||
ret = regmap_read(info->regmap, PPMU_V2_CNTENC, &cntenc);
|
||||
if (ret < 0)
|
||||
return 0;
|
||||
|
||||
cntenc |= (PPMU_CCNT_MASK | (PPMU_ENABLE << id));
|
||||
__raw_writel(cntenc, info->ppmu.base + PPMU_V2_CNTENC);
|
||||
ret = regmap_write(info->regmap, PPMU_V2_CNTENC, cntenc);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
dev_dbg(&edev->dev, "%25s (load: %ld / %ld)\n", edev->desc->name,
|
||||
edata->load_count, edata->total_count);
|
||||
|
|
@ -411,10 +554,19 @@ static int of_get_devfreq_events(struct device_node *np,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int exynos_ppmu_parse_dt(struct exynos_ppmu *info)
|
||||
static struct regmap_config exynos_ppmu_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.val_bits = 32,
|
||||
.reg_stride = 4,
|
||||
};
|
||||
|
||||
static int exynos_ppmu_parse_dt(struct platform_device *pdev,
|
||||
struct exynos_ppmu *info)
|
||||
{
|
||||
struct device *dev = info->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct resource *res;
|
||||
void __iomem *base;
|
||||
int ret = 0;
|
||||
|
||||
if (!np) {
|
||||
|
|
@ -423,10 +575,17 @@ static int exynos_ppmu_parse_dt(struct exynos_ppmu *info)
|
|||
}
|
||||
|
||||
/* Maps the memory mapped IO to control PPMU register */
|
||||
info->ppmu.base = of_iomap(np, 0);
|
||||
if (IS_ERR_OR_NULL(info->ppmu.base)) {
|
||||
dev_err(dev, "failed to map memory region\n");
|
||||
return -ENOMEM;
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(base))
|
||||
return PTR_ERR(base);
|
||||
|
||||
exynos_ppmu_regmap_config.max_register = resource_size(res) - 4;
|
||||
info->regmap = devm_regmap_init_mmio(dev, base,
|
||||
&exynos_ppmu_regmap_config);
|
||||
if (IS_ERR(info->regmap)) {
|
||||
dev_err(dev, "failed to initialize regmap\n");
|
||||
return PTR_ERR(info->regmap);
|
||||
}
|
||||
|
||||
info->ppmu.clk = devm_clk_get(dev, "ppmu");
|
||||
|
|
@ -438,15 +597,10 @@ static int exynos_ppmu_parse_dt(struct exynos_ppmu *info)
|
|||
ret = of_get_devfreq_events(np, info);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to parse exynos ppmu dt node\n");
|
||||
goto err;
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err:
|
||||
iounmap(info->ppmu.base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int exynos_ppmu_probe(struct platform_device *pdev)
|
||||
|
|
@ -463,7 +617,7 @@ static int exynos_ppmu_probe(struct platform_device *pdev)
|
|||
info->dev = &pdev->dev;
|
||||
|
||||
/* Parse dt data to get resource */
|
||||
ret = exynos_ppmu_parse_dt(info);
|
||||
ret = exynos_ppmu_parse_dt(pdev, info);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to parse devicetree for resource\n");
|
||||
|
|
@ -476,8 +630,7 @@ static int exynos_ppmu_probe(struct platform_device *pdev)
|
|||
if (!info->edev) {
|
||||
dev_err(&pdev->dev,
|
||||
"failed to allocate memory devfreq-event devices\n");
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
return -ENOMEM;
|
||||
}
|
||||
edev = info->edev;
|
||||
platform_set_drvdata(pdev, info);
|
||||
|
|
@ -488,17 +641,13 @@ static int exynos_ppmu_probe(struct platform_device *pdev)
|
|||
ret = PTR_ERR(edev[i]);
|
||||
dev_err(&pdev->dev,
|
||||
"failed to add devfreq-event device\n");
|
||||
goto err;
|
||||
return PTR_ERR(edev[i]);
|
||||
}
|
||||
}
|
||||
|
||||
clk_prepare_enable(info->ppmu.clk);
|
||||
|
||||
return 0;
|
||||
err:
|
||||
iounmap(info->ppmu.base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int exynos_ppmu_remove(struct platform_device *pdev)
|
||||
|
|
@ -506,7 +655,6 @@ static int exynos_ppmu_remove(struct platform_device *pdev)
|
|||
struct exynos_ppmu *info = platform_get_drvdata(pdev);
|
||||
|
||||
clk_disable_unprepare(info->ppmu.clk);
|
||||
iounmap(info->ppmu.base);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user