mtd: spi-nor: Add a post BFPT fixup for MX25L25635E
MX25L25635F and MX25L25635E share the same JEDEC-ID, but the F variant supports 4-byte opcodes while the E variant doesn't. We need a way to differentiate those 2 chips and set the SNOR_F_4B_OPCODES flag only for the F variant. Luckily, 4-byte opcode support is not the only difference: Fast Read 4-4-4 is only supported by the F variant, and this feature is advertised in the BFPT table. Use this to decide when to set the SNOR_F_4B_OPCODES flag. Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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@ -1447,6 +1447,31 @@ static int macronix_quad_enable(struct spi_nor *nor);
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.addr_width = 3, \
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.flags = SPI_NOR_NO_FR | SPI_S3AN,
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static int
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mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
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const struct sfdp_parameter_header *bfpt_header,
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const struct sfdp_bfpt *bfpt,
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struct spi_nor_flash_parameter *params)
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{
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/*
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* MX25L25635F supports 4B opcodes but MX25L25635E does not.
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* Unfortunately, Macronix has re-used the same JEDEC ID for both
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* variants which prevents us from defining a new entry in the parts
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* table.
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* We need a way to differentiate MX25L25635E and MX25L25635F, and it
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* seems that the F version advertises support for Fast Read 4-4-4 in
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* its BFPT table.
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*/
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if (bfpt->dwords[BFPT_DWORD(5)] & BFPT_DWORD5_FAST_READ_4_4_4)
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nor->flags |= SNOR_F_4B_OPCODES;
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return 0;
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}
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static struct spi_nor_fixups mx25l25635_fixups = {
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.post_bfpt = mx25l25635_post_bfpt_fixups,
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};
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/* NOTE: double check command sets and memory organization when you add
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* more nor chips. This current list focusses on newer chips, which
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* have been converging on command sets which including JEDEC ID.
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@ -1581,7 +1606,9 @@ static const struct flash_info spi_nor_ids[] = {
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{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
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{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
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SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
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.fixups = &mx25l25635_fixups },
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{ "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
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{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
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{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
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