ath5k: implement multi-rate retry support, fix tx status reporting
Clean up the tx status reporting, fix retry counters (short retries are virtual collisions, not actual retries). Implement multi-rate retry support. This also fixes strong throughput fluctuations with rc80211_pid Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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870abdf671
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2f7fe87034
@ -431,7 +431,9 @@ struct ath5k_tx_status {
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u16 ts_seqnum;
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u16 ts_tstamp;
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u8 ts_status;
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u8 ts_rate;
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u8 ts_rate[4];
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u8 ts_retry[4];
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u8 ts_final_idx;
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s8 ts_rssi;
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u8 ts_shortretry;
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u8 ts_longretry;
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@ -541,6 +541,12 @@ ath5k_pci_probe(struct pci_dev *pdev,
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goto err_irq;
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}
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/* set up multi-rate retry capabilities */
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if (sc->ah->ah_version == AR5K_AR5212) {
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hw->max_altrates = 3;
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hw->max_altrate_tries = 11;
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}
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/* Finish private driver data initialization */
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ret = ath5k_attach(pdev, hw);
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if (ret)
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@ -1173,7 +1179,9 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
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struct sk_buff *skb = bf->skb;
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struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
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unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
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int ret;
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struct ieee80211_rate *rate;
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unsigned int mrr_rate[3], mrr_tries[3];
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int i, ret;
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flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
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@ -1198,6 +1206,22 @@ ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
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if (ret)
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goto err_unmap;
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memset(mrr_rate, 0, sizeof(mrr_rate));
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memset(mrr_tries, 0, sizeof(mrr_tries));
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for (i = 0; i < 3; i++) {
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rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
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if (!rate)
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break;
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mrr_rate[i] = rate->hw_value;
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mrr_tries[i] = info->control.retries[i].limit;
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}
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ah->ah_setup_mrr_tx_desc(ah, ds,
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mrr_rate[0], mrr_tries[0],
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mrr_rate[1], mrr_tries[1],
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mrr_rate[2], mrr_tries[2]);
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ds->ds_link = 0;
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ds->ds_data = bf->skbaddr;
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@ -1814,7 +1838,7 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
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struct ath5k_desc *ds;
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struct sk_buff *skb;
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struct ieee80211_tx_info *info;
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int ret;
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int i, ret;
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spin_lock(&txq->lock);
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list_for_each_entry_safe(bf, bf0, &txq->q, list) {
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@ -1836,7 +1860,25 @@ ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
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pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
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PCI_DMA_TODEVICE);
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info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
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memset(&info->status, 0, sizeof(info->status));
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info->tx_rate_idx = ath5k_hw_to_driver_rix(sc,
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ts.ts_rate[ts.ts_final_idx]);
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info->status.retry_count = ts.ts_longretry;
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for (i = 0; i < 4; i++) {
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struct ieee80211_tx_altrate *r =
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&info->status.retries[i];
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if (ts.ts_rate[i]) {
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r->rate_idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
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r->limit = ts.ts_retry[i];
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} else {
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r->rate_idx = -1;
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r->limit = 0;
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}
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}
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info->status.excessive_retries = 0;
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if (unlikely(ts.ts_status)) {
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sc->ll_stats.dot11ACKFailureCount++;
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if (ts.ts_status & AR5K_TXERR_XRETRY)
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@ -318,6 +318,15 @@ ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
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return 0;
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}
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/* no mrr support for cards older than 5212 */
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static int
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ath5k_hw_setup_no_mrr(struct ath5k_hw *ah, struct ath5k_desc *desc,
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unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
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u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3)
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{
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return 0;
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}
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/*
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* Proccess the tx status descriptor on 5210/5211
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*/
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@ -352,8 +361,10 @@ static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
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AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
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ts->ts_antenna = 1;
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ts->ts_status = 0;
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ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_0,
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ts->ts_rate[0] = AR5K_REG_MS(tx_ctl->tx_control_0,
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AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
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ts->ts_retry[0] = ts->ts_longretry;
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ts->ts_final_idx = 0;
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if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
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if (tx_status->tx_status_0 &
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@ -405,29 +416,43 @@ static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
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AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
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ts->ts_status = 0;
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switch (AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
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case 0:
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ts->ts_rate = tx_ctl->tx_control_3 &
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
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break;
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case 1:
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ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
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ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
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break;
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case 2:
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ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
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ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
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break;
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ts->ts_final_idx = AR5K_REG_MS(tx_status->tx_status_1,
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AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX);
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/* The longretry counter has the number of un-acked retries
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* for the final rate. To get the total number of retries
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* we have to add the retry counters for the other rates
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* as well
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*/
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ts->ts_retry[ts->ts_final_idx] = ts->ts_longretry;
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switch (ts->ts_final_idx) {
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case 3:
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ts->ts_rate = AR5K_REG_MS(tx_ctl->tx_control_3,
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ts->ts_rate[3] = AR5K_REG_MS(tx_ctl->tx_control_3,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
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ts->ts_longretry += AR5K_REG_MS(tx_ctl->tx_control_2,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
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ts->ts_retry[2] = AR5K_REG_MS(tx_ctl->tx_control_2,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
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ts->ts_longretry += ts->ts_retry[2];
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/* fall through */
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case 2:
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ts->ts_rate[2] = AR5K_REG_MS(tx_ctl->tx_control_3,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
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ts->ts_retry[1] = AR5K_REG_MS(tx_ctl->tx_control_2,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
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ts->ts_longretry += ts->ts_retry[1];
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/* fall through */
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case 1:
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ts->ts_rate[1] = AR5K_REG_MS(tx_ctl->tx_control_3,
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
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ts->ts_retry[0] = AR5K_REG_MS(tx_ctl->tx_control_2,
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AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
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ts->ts_longretry += ts->ts_retry[0];
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/* fall through */
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case 0:
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ts->ts_rate[0] = tx_ctl->tx_control_3 &
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AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
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break;
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}
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@ -653,7 +678,7 @@ int ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
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} else {
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ah->ah_setup_rx_desc = ath5k_hw_setup_rx_desc;
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ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
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ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_mrr_tx_desc;
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ah->ah_setup_mrr_tx_desc = ath5k_hw_setup_no_mrr;
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ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
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}
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